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Hardware Register to indicate SPI Transfer Complete or maybe SPI Busy? (Non-MIBSPI mode)

Hello,

We are using the '3137 PGE package and the SPI CS's are all going through decoders since we ran out of I/O's; so none of our SPI slaves have ENA.

Is there a hardware register that will indicate when the SPI CLK or main CS for the channel goes inactive indicating the SPI transfer is done?

Could be SPI busy bit so to speak but I don't see anything like that in the TRM.  I have seen the spiNotification discussion and I know this has been discussed in the past - and I suppose the necessity of having spiNotification answers this - but wanted to ask anyway in case I have missed something in the register definitions.

Thanks In Advance,

John W.

  • Hi John,

    Normally you would simply use the RXINTFLAG flag in SPIFLG register to determine when to service the SPI.

    Are you running into some issue where you are manipulating GIO after the transfer to control a decoder, and having trouble
    with timing?

    If so you can read the pin state from the SPIPC2 register to directly check the state of any of the chip select pins.

    The SPI also supports decoded encoded chip selects and may be able to do some of this for you automatically.
    The chip selects are just a pattern as far as the SPI is concerned. You write the pattern you want on the pins when the SPI is idle into the
    SPIDEF (default chip select register) and when you transfer you write the pattern that you want on the chip select pins during the transfer
    into the CSNR field of the SPIDAT1 register.

    There is no requirement that the CSNR field or CSDEF field be any sort of '1 hot' or complement of '1 hot' pattern.

    So you could use 3 chip select lines to control an 8:1 decoder and use 1 chip select as the 'strobe' that passes through this decoder.
    The advantage of this method is that the SPI itself would handle the timing of changing of these signals as part of the data transfer.

    Best Regards,
    Anthony
  • Hello Anthony,

    Yes - timing is an issue but the SPIPC2 register should be fine for this.

    Thanks for that and the suggestions.
    Best Regards,
    John W.