Hi,
I have 2 questions relating to multi-buffered SPI.
1. When the MIBSPIE[0] is set, can the SPI module still be used in compatibility mode? i.e. will a write to DAT1 still result in transmission of SPI data? I have an SPI ADC which I would like to configure in compatibility mode, then handle reading of conversions using multi-buffered mode, with TG being triggered by a falling edge of the ADC's DRDY output which is connected to GIOA[7].
2. What is required in the BUFID field in DMAxCTRL register? I have a single transfer group which contains 4 bytes of data that need to be clocked out of the TMS570 in order to read back 4 bytes of conversion data from the ADC which I then wish to DMA to a circular buffer which will hold conversion data ready to be processed periodically by the application. This TG is simply triggered repeatedly by the DRDY signal from the ADC. Does BUFID correspond to PSTARTx in TGxCTRL or is this something different?
I have successfully used DMA with data received via SCI interface so I think I am OK with that side of things, it is just mapping the MIBSPI DMA requests to the DMA module channels that I am not sure about.
Thank you for your help.
Mark.