RM48L952ZWT & HalCoGen: VIM - Configure Interrupt order and issues

Hi Sarah,

  1. The HalCoGen currently does not support GUI based channel remapping. You will need to use vimChannelMap() API in your application code.

  2. If you look at channel 9 in the VIM RAM tab, the ISR vector is called gioHighLevelInterrupt. This is what you want to remap to channel 2. You do NOT need to change the VIM RAM tab. What you want is to call the vimChannelMap() API. This is how you do it as follows.

  vimChannelMap(9,2,&gioHighLevelInterrupt);

  The API will map request 9 which is connected to GIO high level interrupt request to channel and write the corresponding ISR address to VIM RAM for you. See below API for detail. 

  If you want to map request 23 to channel 2 then you will call:

   vimChannelMap(23,2,&gioLowLevelInterrupt);

void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
{
    uint32 i,j;
    i = channel >> 2U;              /* Find the register to configure */
    j = channel - (i << 2U);        /* Find the offset of the type    */
    j = 3U - j;                     /* reverse the byte order         */
    j = j << 3U;                    /* find the bit location          */

    /*Mapping the required interrupt request to the required channel*/
    vimREG->CHANCTRL[i] &= ~(uint32)((uint32)0xFFU << j);
    vimREG->CHANCTRL[i] |= (request << j);

    /*Updating VIMRAM*/
    vimRAM->ISR[channel + 1U] = handler;
}

  3. Once the CPU enters the ISR for gioHighLevelInterrupt ISR, the application can then determine whether the interrupt is coming from BUSOK or ACOK. 

4. For the typos in the VIM RAM tab, I will forward to HalCoGen team for fixing. 

Re-pasting the vimChannelMap() API.

void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler)
{
uint32 i,j;
i = channel >> 2U; /* Find the register to configure */
j = channel - (i << 2U); /* Find the offset of the type */
j = 3U - j; /* reverse the byte order */
j = j << 3U; /* find the bit location */

/*Mapping the required interrupt request to the required channel*/
vimREG->CHANCTRL[i] &= ~(uint32)((uint32)0xFFU << j);
vimREG->CHANCTRL[i] |= (request << j);

/*Updating VIMRAM*/
vimRAM->ISR[channel + 1U] = handler;
}

Hi Charles, thank you for the explanation, just how would I determine which interrupt hit, which in this case is BUSOK or ACOK?

void gioHighLevelInterrupt()
{
// Is BUSOK?
if (???)
{
}
// Is ACOK
else if (???)
{
}
}

What do I call to find out what generated the interrupt?

Hi Sarah,

  Your BUSOK and ACOK will be connected to two different GIOA pins. You may also be using the other pins of GIOA for different things. You question is what happens when some of them or all of them all generate the interrupt at the same time, right? The GIO module contains an offset register which indicates the highest pending priority of interrupt. For example, if BUSOK is connected GIOA[0] and ACOK is connected to GIOA[1] and both of them interrupt at the same time, the GIO module will show the highest pending interrupt in the offset register for BUSOK. See below userguide description for the GIO offset register. There is also an entire sub-section in the GIO userguide that talks about how interrupt is handled. 

#pragma CODE_STATE(gioHighLevelInterrupt, 32)
#pragma INTERRUPT(gioHighLevelInterrupt, IRQ)

void gioHighLevelInterrupt(void)
{
    uint32 offset = gioREG->OFF1;

/* USER CODE BEGIN (14) */
/* USER CODE END */
	
	if (offset != 0U)
	{
		offset = offset - 1U;
		if (offset >= 8U)
		{
			gioNotification(gioPORTB, offset - 8U);
		}
		else
		{
			gioNotification(gioPORTA, offset);
		}
	}
/* USER CODE BEGIN (15) */
/* USER CODE END */

}

See above code generated by HalcoGen. The first thing it does is find out the offset by reading gioREG->OFF1. From the offset it knows which interrupt is of the highest priority from GIO module. It then calls gioNotification() b passing the offset argument. In the gioNotification() your application needs handle how you want for each interrupt like BUSOK or ACOK. 

void gioNotification(gioPORT_t *port, uint32 bit)
{
/*  enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (22) */
	
	if (bit == 0 ) { // assume BUSOK is 0
		// do something for BUSOK
	} else if (bit == 1) { // assume ACOK is 1
		// do something for ACOK
	}
/* USER CODE END */
}

Hi Charles,

I see

VIM 64 sciHighLevelInterrupt

VIM 74 sciLowLevelInterrupt

Which one, or another VIM and then why, would allow me to trap COM1/2 RX/TX. I configured SCI1/2 for my COM1/2 needs earlier. I saw no other SCI entries.

How would I trap which interrupt? Here is some pseudo code that I just wrote using the API as a guide. I need the fill-in stuff.

void sciHighLevelInterrupt()

{

     // COM1: RX

    if (?????)

    {

           do

           {

                     ??? = sciIsRxReady(???);

                     if (??? == ???)

                         break;

                  UINT32 byReceive1 = sciReceiveByte(???);

           } while (TRUE);

    }

    // COM2: RX

    // COM1: TX

    if (?????)

    {

                ??? = sciIsTxReady(???);

                 if (??? == ???)

                 {

                     uint32 sendLength = 0; // whatever here

                    uint8[] sendData = new uint8[sendLength];

                     sciSend(???, sendLength, sendData);

                }

    }

    // COM2: TX

}

More Help Documentation Corrections:

example_sci_uart_9600.c

   sciInit();

    /* initialize sci/sci-lin    */

                   /* even parity , 2 stop bits */

       while(1)

       /* continious desplay        */

   {      sciDisplayText(UART,&TEXT1[0],TSIZE1);

  /* send text code 1 */

     sciDisplayText(UART,&TEXT2[0],TSIZE2);

  /* send text code 2 */

     sciDisplayText(UART,&TEXT3[0],TSIZE3);

  /* send text code 3 */

       wait(200);

   };

Hi Sarah,

  I was in training the entire day. Just got time to reply now. 

  I'm not clear on your question. Are you asking where is the SCI in the VIM Channel tab? If this is the question then you want to look for LIN module. LIN module is mapped to VIM channel 13 and 27. The LIN module in RM48x device can operate in SCI mode. It is considered as SCI2 when in SCI mode. So you want to click on channel 13 and 27 to enable the interrupt for SCI2.

  The way the interrupt is handled is very similar to GIO where you will determine the highest pending interrupt by reading the offset register. Below is a snippet of the SCI interrupt ISR.

#pragma CODE_STATE(linHighLevelInterrupt, 32)
#pragma INTERRUPT(linHighLevelInterrupt, IRQ)

/* SourceId : SCI_SourceId_021 */
/* DesignId : SCI_DesignId_017 */
/* Requirements : HL_SR245, HL_SR246 */
void linHighLevelInterrupt(void)
{
    uint32 vec = scilinREG->INTVECT0;
	uint8 byte;
/* USER CODE BEGIN (35) */
/* USER CODE END */

    switch (vec)
    {
    case 1U:
        sciNotification(scilinREG, (uint32)SCI_WAKE_INT);
        break;
    case 3U:
        sciNotification(scilinREG, (uint32)SCI_PE_INT);
        break;
    case 6U:
        sciNotification(scilinREG, (uint32)SCI_FE_INT);
        break;
    case 7U:
        sciNotification(scilinREG, (uint32)SCI_BREAK_INT);
        break;
    case 9U:
        sciNotification(scilinREG, (uint32)SCI_OE_INT);
        break;

    case 11U:
        /* receive */
			byte = (uint8)(scilinREG->RD & 0x000000FFU);

            if (g_sciTransfer_t[1U].rx_length > 0U)
            {
                *g_sciTransfer_t[1U].rx_data = byte;
                /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
				g_sciTransfer_t[1U].rx_data++;
                g_sciTransfer_t[1U].rx_length--;
                if (g_sciTransfer_t[1U].rx_length == 0U)
                {
                    sciNotification(scilinREG, (uint32)SCI_RX_INT);
                }
            }
        break;

    case 12U:
        /* transmit */
		/*SAFETYMCUSW 30 S MR:12.2,12.3 <APPROVED> "Used for data count in Transmit/Receive polling and Interrupt mode" */
		--g_sciTransfer_t[1U].tx_length;
        if (g_sciTransfer_t[1U].tx_length > 0U)
        {
			uint8 txdata = *g_sciTransfer_t[1U].tx_data;
            scilinREG->TD = (uint32)(txdata);
            /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
			g_sciTransfer_t[1U].tx_data++;
        }
        else
        {
            scilinREG->CLEARINT = (uint32)SCI_TX_INT;
            sciNotification(scilinREG, (uint32)SCI_TX_INT);
        }
        break;

    default:
        /* phantom interrupt, clear flags and return */
        scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U;
        break;
    }
/* USER CODE BEGIN (36) */
/* USER CODE END */
}

You also want to reference the userguide for the different offset values. See below. So if the offset register reads 10 it means that you are getting an receive interrupt meaning the UART is receiving a character. 11 means that you have just transmitted an char on the TX line.

No worries on the in meeting. I have been reading and pushing forward.

We do not use SCILIN, just SCI for COM1 and COM2, both at 9600 baud.

I do see the sciNotification() function in notification.c.


void sciNotification(sciBASE_t *sci, uint32 flags)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (29) */
// Only trap COMM communication.
if (sciREG != sci)
return;

/* USER CODE END */
}

The documentation states:

Parameters
[in] sci - sci module base address
[in] flags - copy of error interrupt flags

How can I tell which byte gets received from SCI1 and which from SCI2?

I assume that the argument for sciIsRxReady(), sciSend(), and the others is sciREG, but that does not indicate SCI1 (COM1) or SCI2 (COM2)

HI Sarah,

  The LINSCI in SCI mode is the SCI2. The regular SCI is the SCI1.

void sciNotification(sciBASE_t *sci, uint32 flags) 
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (29) */
// Only trap COMM communication.
if (sci == scIREG) {

// my COM1 stuffs

} else if ( sci == scilinREG) {

// my COM2 stuffs

}

/* USER CODE END */
}

There appears to be a conflict between the EE requirement and what I now understand:

1.8.4.4. The COM1 Rx interrupt is the next priority, and is SCI Level 0, which makes it Interrupt Request 64 (decimal). So write 0x40 to 0xxFFF7E586.
1.8.4.5. The COM2 Rx interrupt is the next priority, and is LIN/SCI Level 0, which makes it Interrupt Request 13 (decimal). So write 0x0D to 0xxFFF7E485.
1.8.4.6. The COM1 Tx interrupt is the next priority, and is SCI Level 1, which makes it Interrupt Request 74 (decimal). So write 0x4A to 0xxFFF7E584.
1.8.4.7. The COM2 Tx interrupt is the next priority, and is LIN/SCI Level 1, which makes it Interrupt Request 27 (decimal). So write 0x1B to 0xxFFF7E483.

I coded:

// Initailize: VIM Table
vimInit();
vimChannelMap(9,2,&gioHighLevelInterrupt);
vimChannelMap(2,3,&rtiCompare0Interrupt);
vimChannelMap(64,4,&sciHighLevelInterrupt); // COM1 and COM2

You had me use an if-statement to tell which COM port. Do I now use 2 different interrupts?

Also, are interrupts 74 and 27 the TX interrupts? I thought that I do not deal with TX interrupts, as I just call sciSend() to do the honors.

Would that make the code the following?

// Initailize: VIM Table
vimInit();
vimChannelMap(9, 2, &gioHighLevelInterrupt);
vimChannelMap(2, 3, &rtiCompare0Interrupt);
vimChannelMap(64, 4, &sciHighLevelInterrupt); // COM1 RX: SCI Level 0, which makes it Interrupt Request 64
vimChannelMap(13, 5, &linHighLevelInterrupt); // COM2 RX: LIN/SCI Level 0, which makes it Interrupt Request 13
vimChannelMap(74, 6, &sciLowLevelInterrupt); // COM1 TX: SCI Level 1, which makes it Interrupt Request 74
vimChannelMap(27, 7, &linLowLevelInterrupt); //COM2 TX: LIN/SCI Level 1, which makes it Interrupt Request 27

// Enable COM1/2 notifications.
sciEnableNotification(sciREG, SCI_RX_INT); // COM1 Receive buffer ready
sciEnableNotification(sciREG, SCI_TX_INT); // COM1 Transmit buffer ready
sciEnableNotification(sciREG, SCI_OE_INT); // COM1 Overrun error
sciEnableNotification(scilinREG, SCI_RX_INT); // COM2 Receive buffer ready
sciEnableNotification(scilinREG, SCI_TX_INT); // COM2 Transmit buffer ready
sciEnableNotification(scilinREG, SCI_OE_INT); // COM2 Overrun error


I see that both sciHighLevelInterrupt() and sciLowLevelInterrupt() have receive (vector 11) and transmit (vector 12) for COM1 and both linHighLevelInterrupt() and linLowLevelInterrupt() have receive (vector 11) and transmit (vector 12), which call sciNotifcation()? What is the difference?

COM1:
// Each called from sciHighLevelInterrupt() and sciLowLevelInterrupt()
sciNotification(sciREG, (uint32)SCI_RX_INT);
sciNotification(sciREG, (uint32)SCI_TX_INT);

COM2:
// Each called from linHighLevelInterrupt() and linLowLevelInterrupt()
sciNotification(scilinREG, (uint32)SCI_RX_INT);
sciNotification(scilinREG, (uint32)SCI_TX_INT);

Based on your EE requirements:

1.8.4.4. The COM1 Rx interrupt is the next priority, and is SCI Level 0, which makes it Interrupt Request 64 (decimal). So write 0x40 to 0xxFFF7E586.
1.8.4.5. The COM2 Rx interrupt is the next priority, and is LIN/SCI Level 0, which makes it Interrupt Request 13 (decimal). So write 0x0D to 0xxFFF7E485.
1.8.4.6. The COM1 Tx interrupt is the next priority, and is SCI Level 1, which makes it Interrupt Request 74 (decimal). So write 0x4A to 0xxFFF7E584.
1.8.4.7. The COM2 Tx interrupt is the next priority, and is LIN/SCI Level 1, which makes it Interrupt Request 27 (decimal). So write 0x1B to 0xxFFF7E483

You need to have the following HalCoGen config. The COM1 using SCI1,  the RX interrupt needs to be mapped to level0 (request 64) and TX mapped to level1 (request 74). I don't know if you are going to enable other interrupts like frame error, break, and etc. You need to make decision on how and if you want to handle these errors. If you want to handle all the errors then you will enable all of them. You also need to decide whether these error interrupts go to level0 or level1. Similarly you will do the same for SCI2 which is the LinSCI. 

The HalcoGen just generates template code for you. With the above HalcoGen config the sciHighLevelInterrupt() will only be entered when you have RX interrupt. The TX interrupt will go to sciLowLevelInterrupt. If you know for sure that you will only have RX interrupt for sciHighLevelInterrupt() then you can even remove the code like below if you want. If you don't want to alter the generated code that is fine too. Even though the sciHighLevelInterrupt() has the switch statements for each type of interrupt those will never be entered except the RX. 

void sciHighLevelInterrupt(void)
{
    uint32 vec = sciREG->INTVECT0;
	uint8 byte;
/* USER CODE BEGIN (28) */
/* USER CODE END */

    switch (vec)
    {


    case 11U:
        /* receive */
         byte = (uint8)(sciREG->RD & 0x000000FFU);

            if (g_sciTransfer_t[0U].rx_length > 0U)
            {
                *g_sciTransfer_t[0U].rx_data = byte;
                /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
				g_sciTransfer_t[0U].rx_data++;
                g_sciTransfer_t[0U].rx_length--;
                if (g_sciTransfer_t[0U].rx_length == 0U)
                {
                    sciNotification(sciREG, (uint32)SCI_RX_INT);
                }
            }
        break;


    default:
        /* phantom interrupt, clear flags and return */
        sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303U;
        break;
    }
/* USER CODE BEGIN (29) */
/* USER CODE END */
}

Use this config instead. I got the high and low interrupt opposite in the last post. Here I enable all interrupt sources. However, I only map RX to high level (level0) and everything else to low level (level1).

I wanted to enable the overrun enable. Does it matter which level I choose?

Also, you never responded to the 13ms sample time on the other thread.

You application needs to decide what priority level you need for the overrun error. I will have all errors mapped to high level. They are not supposed to occur. But if they do occur you want to handle them asap in my opinion.

The sampling time depends on your external impedance to the ADC input. I won't know this. I'm just questioning if your EE really wants 4096 ADC cycles for samplign window. You need to discuss with your EE what is appropriate. Here is one app note that will help you and your EE to determine what sample window is needed. www.ti.com/.../spna118b.pdf

I have to clear and then enable for writing.

1.8.6.5. Clear any COM1 pending interrupts by writing 0x07001F0F to the SCI Flags Register (SCIFLR at 0xFFF7E51C).
1.8.6.6. Enable the COM1 Rx interrupt by writing 0x00000200 to the SCI Set Interrupt Register (SCISETINT at 0xFFF7E50C).

I see that in the case of default case, there is this code:

linHighLevelInterrupt() : default case
scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U;
linLowLevelInterrupt(): default case
scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U;
sciLowLevelInterrupt(): default case
sciREG->FLR = sciREG->SETINTLVL & 0x07000303U;
sciHighLevelInterrupt(): default case
sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303U;

Do I just call for the following to clear COM1 and COM2 respectively, or do I call something else?
sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303U;
scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U;

I see that the sciInit() does the following, so I do not need to do anything to enable interrupts.

/** - set interrupt enable */
sciREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */
| (uint32)((uint32)0U << 25U) /* Overrun error */
| (uint32)((uint32)0U << 24U) /* Parity error */
| (uint32)((uint32)1U << 9U) /* Receive */
| (uint32)((uint32)0U << 1U) /* Wakeup */
| (uint32)((uint32)0U << 0U); /* Break detect */
/** - set interrupt enable */
scilinREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */
| (uint32)((uint32)0U << 25U) /* Overrun error */
| (uint32)((uint32)0U << 24U) /* Parity error */
| (uint32)((uint32)1U << 9U) /* Receive */
| (uint32)((uint32)0U << 1U) /* Wakeup */
| (uint32)((uint32)0U); /* Break detect */

When an interrupt occurs it will set the corresponding bit in the FLR register, i.e. an OE or an RX bit. You can have multiple bits set at the same time. if you read the below userguide, the last bullet says for each register bit, the bit can be cleared by reading the offset register. When you enter sciHighLevelInterrupt() the very first thing it does is to read the offset register. Let's say you have both OE and RX bits set but OE interrupt has higher priority than RX so the offset register will read 9 rather than 11. As soon as you read the offset register the OE bit in the FLR register will be cleared. You don't need to manually clear it. If you want to clear the bit manually, perhaps you are not using interrupt mode but rather polling mode then you will write sciREG->FLR = 0x2000000 to clear the OE bit since OE bit is bit 25. You don't want to clear other bits because you have not serviced other interrupts yet. 

Reading your pasted HalCoGen generated code, the sciInit() did not enable interrupt for TX. Unless you do not need TX interrupt, you don't need to enable TX interrupt. If you need to have TX interrupt then you need to do something like sciEnableNotification(sciREG, SCI_TX_INT) to enable it.