SafeTI Library

Hi Screekanth,
Can you read out the IFSR (instruction fault status register) and IFAR (instruction fault address register) inside the CPU? These registers show the cause of the prefetch abort.

This diagnostic 5 is testing the address tag register associated with the flash controller pipeline buffer. My doubt is that you might be in pipeline mode already and you are trying to run diagnostic of the address tag register. There could be some disturbance to the pipeline logic as a consequence. I wonder if you first disable pipeline mode before you run diagnostic mode 5 to see of any difference. To disable pipeline mode you just clear the bit 0 of the FRDCNTL register of the flash controller.

Hi Charles,

I have changed the code as below as per your comments.

// Disable pipelining
sl_flashWREG->FRDCNTL &= (~0x00000001);

retVal = SL_SelfTest_Flash(FLASH_ECC_ADDR_TAG_REG_MODE, TRUE, &failInfoFlash);
INCREMENT_PASS_FAIL_COUNTER(failInfoFlash, retVal);
// Enable pipelining
sl_flashWREG->FRDCNTL |= 0x00000001;

I do not get any exception now. is this expected? I am assuming that i should see void _excpt_vec_abort_data() exception in order to diagnose.

please let me know your comments.

Thanks & Best Regards,
Sreekanth Reddy challa

Hi Charles,

I have changed the code as below as per your comments. 

// Disable pipelining
sl_flashWREG->FRDCNTL &= (~0x00000001);

retVal = SL_SelfTest_Flash(FLASH_ECC_ADDR_TAG_REG_MODE, TRUE, &failInfoFlash);
INCREMENT_PASS_FAIL_COUNTER(failInfoFlash, retVal);
// Enable pipelining
sl_flashWREG->FRDCNTL |= 0x00000001;

I do not get any exception now. is this expected? I am assuming that i should see void _excpt_vec_abort_data() exception in order to diagnose.

please let me know your comments.

Thanks & Best Regards,
Sreekanth Reddy challa

Hi Sceekanth,
I think this is expected. Think of the pipeline buffer as a simple cache where it will store the most recent read data. Corresponding to the pipeline buffer is a tag address. When CPU tries to read from the flash the flash controller compares the CPU address against the address that is stored in the address tag register. If there is match it means the data is already in the buffer so there is no need to read directly from the flash memory which will take several wait states. Here you are running diagnostic by injecting test data into the address tag register while the CPU in parallel is reading code from flash at the same time. Both the test logic and the read logic are kind of fighting to use the pipeline buffer at the same time. The diagnostic test data that is being applied could be mis-interpreted by the read logic as the intended data. With all these, I think this is why an abort results and if you disable pipeline mode then it went through.

Hi Charles,

Thanks for the feedback and explanation. It solved the problem.

Best Regards,
Sreekanth Challa