Hi,
I am testing freertos+lwip on the RM57L843. Cache is enabled. I focus on the cache attribute i.e. Write-through or write-back.
Here the MPU I means the MPU in the core not the NMPU like the thread(I paste the URL in the end) discussed.
I configure the memory area(pbuf) used by the lwip task as the WT to enable the uSCU to keep the cache coherency(for CPU-reading) and enable EMAC DMA get the lastest data(for CPU-writing).
Now I have a question, there are several tasks in my system not just the lwip task, what will happen if the EMAC DMA is writing in-coming package into the memory while a task happened, I mean that the cache policy maybe changed(I am not sure about this, because another task will not specify the memory area used by the lwip(EMAC DMA)) and the the WT+uSCU mechanism maybe failed? or the EMAC DMA will not be affected?