This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Regarding ESM low level interrupt for Single bit SRAM ECC error

Hi,

I would like to generate the esm low level interrupt group 1 channel 26 (SRAM EVEN bank correctable interrupt). I am using the below function provided by SafeTI library to generate the interrupt. I have configured ESM properly to generate the interrupt.

SL_SelfTest_SRAM(SRAM_ECC_1BIT_FAULT_INJECTION, TRUE, &failInfoTCMRAM);

When i run the above function, the SERR bit in the RAMERRSTATUS register sets to "1".  Still i do not get the interrupt.  I am in debug mode. 

Does being in debug mode fails to trigger interrupt?

Thanks & Best Regards,

Sreekanth challa

  • No being in debug mode doesn't block interrupts unless you are single stepping.
  • Sreekanth,

    Anthony is right interrupts aren't blocked in debug mode, but ECC errors are "blocked":

    5.6.1 System Emulation
    During emulation when SUSPEND signal is high, the data read from memory is still passed to SECDED
    for correction if ECC_ENABLE is active. If a correctable error is detected then it is corrected but error
    event is not generated and error occurrence counter is not incremented if in profiling mode. If a double
    error is detected then the raw data is returned without generating double error signal.
    The SUSPEND signal can be disable by using the SUSP_IGNR bit in FEDACCTRL1 register. The
    SUSPEND signal should not be confused with the suspend_now operation for the FSM.
    6.6 Emulation / Debug Mode Behavior
    The following describes the behavior of the TCRAM Module when in debug mode:
    • The RAMOCCUR register continues to count the single-bit error corrections performed by the Cortex-
    R4F CPU's SECDED logic.
    • No single-bit error interrupt is generated nor is any single-bit error address captured even when the
    RAMOCCUR counter reaches the programmed single-bit error correction threshold.
    • No uncorrectable error interrupt is generated nor is any double-bit error address captured.
    • No address parity error interrupt is generated nor is any parity error address captured.
    • The RAMUERRADDR register is not cleared by a read in debug mode.
    – That is, if a double-bit error address is captured and is not read by the CPU before entering debug
    mode, then it remains frozen during debug mode even if it is read.
    • The RAMPERRADDR register is not cleared by a read in debug mode.

    However, I think this is only true when single stepping or accessing the memory from the debug window trough the CPU.

    Did you tried what happens if you aren't connected with the debugger, is the interrupt taken in this case?

    Thanks,
    Christian

  • Hi Anthony & Christian,

    Thanks for your inputs. I am able to generate the ESM interrupt with ECC 1 bit fault injection self test provided in the safety library. (The following is the function)

    SL_SelfTest_SRAM(SRAM_ECC_1BIT_FAULT_INJECTION, TRUE, &failInfoTCMRAM);

    Thanks & Best Regards,
    Sreekanth challa