TMS570LC4357 controller with Phy DP82640

Lars,

Not sure what the issue is. We have a low cost kit w. the DP83630 though and an lwIP example.
processors.wiki.ti.com/.../LAUNCHXL2-570LC43 .. so for about $29 you could get some platform to compare against.

It really could be a lot of things - strap pins on the phy, pullup issue, pin muxing issue, etc.

Especially on the 4357 where the ethernet pins have 2 locations and you have not only *output* muxing to worry about but also *input muxing* ...

You might start by checking which balls you have wired up to the phy, and then which pinmux settings you have on the input and output mux tabs.

-Anthony

also make sure you do not start MDIO accesses too quickly after releasing the phy from reset or powering on. See the phy datasheet but there is some time required to allow the phy to reset itself before you can start toggling MDC.

Hi Anthony,
yes I have here the development KIT "TMS570LC43x HDK" and there the SW and HW is working fine. So I copied the schematic for the phy in my own layout.

I have two differences between the "TMS570LC43x HDK" layout and my own layout:

1.) I forgot the three resistors for the Strap Pins "LED_LINK", "LED_SPEED", "LED_ACT". But as I understand this is not the reason why I do not get a Phy ID. These pins are used for "AUTO-NEGOTIATION ENABLE".

2.) In the schematic of the "TMS570LC43x HDK" is Strongly Recommend:
              1. Add a 2.2K ohms pull-down resistors to RXD_2 and RXD_3 signals.
              2. Add a 2.2K ohms pull-up resistor to CRS/CRS_DV signal

These pull ups and downs are included in my layout.

I have a delay of 1sec. between "Reset" and "Start MDC". So my first question is:

How can I see if the PHY is running ? If I look in the datasheet --> if bit 29 in the register "MDIO_USERACCESS0" (Base Adr + 0x80) is set the Phy ack the read transaction. Right ? If the Register is 0x2xxx xxxxx --> that means my phy is running.

The next question is:

What is the minimum configuration of the phy to read the phy ID ? I guess the serial Interface must run (MDC and MDIO) and the phy must run, or?

And my last question:

Is there a timing requirement between power up and reset ?

Best regards

Lars

Hi Lars

Lars Guenther said:

yes I have here the development KIT "TMS570LC43x HDK" and there the SW and HW is working fine. So I copied the schematic for the phy in my own layout.

Then the same software should run.. Have you tried that?  It would cut a lot of software related variables out of the picture if you could do that.

Lars Guenther said:

How can I see if the PHY is running ? If I look in the datasheet --> if bit 29 in the register "MDIO_USERACCESS0" (Base Adr + 0x80) is set the Phy ack the read transaction. Right ? If the Register is 0x2xxx xxxxx --> that means my phy is running.

Well I think it means that the phy ACKnowledged the read.  But you'd need to issue a read by setting up "WRITE=0", then the PHYADDR, and REGADDR.  Then write a '1' to the "GO" bit in bit 31.

If you open CCS's register view on MDIO while you are in a debug session you can expand the USER Access field and very easily poke different REGADDR, PHYADDR into USER ACCESS 0 then write a '1' to 'GO' and watch it do the access.

I take it you can't even read the PHY ID from registers 0x2, 0x3?

Lars Guenther said:

What is the minimum configuration of the phy to read the phy ID ? I guess the serial Interface must run (MDC and MDIO) and the phy must run, or?

not sure I understand this question.  it could be expanded to include things like the TMS570 device needs to be initialized so the MDIO module is enabled, the pinmux needs to be set to the correct pins for MDIO [there are 2 possible pinouts and the default *is not* correct if you followed the HDK schematic],  there is a pullup on the PCB on the MDIO line, the input mux is set correctly (different tab in PINMUX but needs to be set to read data back from the correct pin),  the clock frequency of the chip and the derived MDIO clock frequecy need to be < 2.5MHz, the phy needs to be released from reset, you need to meet all the other specs for the phy power on sequence [like the delay between power on and first MDC clock edge...].   

A lot really could be going wrong so I'd try:

  a) running the software that works on your HDK.. if you copied the schematic hopefully it would work unmodified

  b) put a scope or logic  analyzer  on the MDC/MDIO lines so you can see what's going on - and then using this

      information try to home in on what the problem might be   [reduce the problem space].

Thanks and Best Regards,

Anthony

Hi all,

I was looking on the wrong side. I was thinking if the Ack Bit (Bit 29) is set in the register "MDIO_USERACCESS0" the seriell communciation via MDIO and MDC is running. But I used the wrong pins on the controller side.

But now I have one question.

Why could I see the Ack Bit in the register "MDIO_USERACCESS0" ?

Best regards

Lars