Peripheral Central Resource (PCR) Access Management

Arriy

I'm reading "Safety Manual for TMS570LS31x and TMS570LS21x Hercules™ ARM®-Based Safety Critical Microcontrollers(Literature Number: SPNU511D)".

I have a question in chapter "7.94 Peripheral Central Resource (PCR) Access Management".

I think,after setting unused features is disable,access to this features,detect bus error.

This system has bus error report to bus master.

It is possible to check bus error occurred by SW or HW ?

Is this system has bus error flag ?

over 7 years ago

0 Anthony F. Seely over 7 years ago

TI__Guru 65480 points

This should result in a data abort exception if the CPU is the bus master and tries to access something you disabled.

0 Arriy over 7 years ago in reply to Anthony F. Seely

Expert 1720 points

Hi,Anthony

Thank you your answer.

Is this microcontroller have an address to be accessed by a data abort ?

If have,please tell me the address.

0 Anthony F. Seely over 7 years ago in reply to Arriy

TI__Guru 65480 points

Yes,

I would suggest reading "ARM® Cortex®-R Series Version: 1.0 Programmer’s Guide" which is a document from ARM Ltd. ARM DEN 0042A

It will cover a lot of these basic questions about the CPU itself.

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Peripheral Central Resource (PCR) Access Management