Primary SRAM BTCM Address and Control Bus Parity fault injection

Arriy

I am reading "Safety Manual for TMS570LS31x and TMS570LS21 x Hercules ARMR-Based Safety Critical Microcontrollers (Literature Number: SPNU511D)".

I have question in chapter "7.99 Primary SRAM BTCM Address and Control Bus Parity".

Is It mechanism possible to fault injection ?

over 7 years ago

0 Bob Crosby over 7 years ago

TI__Guru 72500 points

The functioning of the parity scheme is checked by programming the ADDR Parity override key of the RAMCTL register to 0xD, thereby making the wrapper check parity in a scheme opposite to that of the address parity generation logic.

0 Haggy over 7 years ago in reply to Bob Crosby

Intellectual 440 points

Hi Bob Crosby,

I have additional questions.
Set the 0xD to ADDR PARITY OVERRIDE bit of RAMCTRL register.
Then, an error occurs even if the read or write?

0 Bob Crosby over 7 years ago in reply to Haggy

TI__Guru 72500 points

Yes, an error will occur on any read or write to the BTCM RAM.

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Primary SRAM BTCM Address and Control Bus Parity fault injection