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When Livelock error flag is set ?

Other Parts Discussed in Thread: TMS570LS3137, HALCOGEN

I use TMS570LS3137.

What are the conditions for setting flags ?

I want to know the operation of the system when Livelock occurs.

In order to I execute fault injection test.

  • See SPNU511D 7.41 Flash Hard Error Cache and Livelock for a description. No fault injection test is mentioned.
    The condition itself is a combination of ECC errors together in memory and it always causes the CPU to reset to recover.
    I suppose you could program your flash with ECC errors that would cause a livelock but I am not sure this is a good idea; and it isn't indicated in SPNU511D as something to do.
  • Hi,Anthony.

    Thank you your answer.

    When an livelock error actually occurs, I want to exective a failure insertion test in order to ascertain the movement of the system.

    Is there no need to perform this failure insertion test ?

  • Arriy,

    I don't understand the question; normally I think of the tests where you inject a failure to check that the diagnostic mechanism is functional as something you do ahead of an actual failure, not as a response to a failure like livelock.

    -Anthony
  • Hi,Anthony.

    Thank you your answer.

    I want to test fail processing when liveLock occurs in functional test
    So, please tell me how to make LiveLock.

    Best Regards.

  • Hi Arriy,

    We don't have any canned recipe for Livelock creation - it is listed in the SafeTI Diganostic library as something not implemented. 

    There is a description of the type of ECC error combination that creates a livelock in SPNU511D 7.41 Flash Hard Error Cache and Livelock

    So you would need to create this type of ECC error conditon, perhaps using linker generated ECC, to synthesize a livelock. 

    -Anthony

  • Hi,Anthony.

    I have read Safety Manual(SPNU511D).

    In "7.41 Flash Hard Error Cache and Livelock" describes how Livelock error occur.

    • Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
    • A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload

    I don't know how to above realize it.

    Please tell me how to make this.

  • Hi,Anthony.


    I have read Safety Manual(SPNU511D).
    In "7.41 Flash Hard Error Cache and Livelock" describes how Livelock error occur.

    • Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
    • A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload


    I don't know how to above realize it.


    Please tell me how to make this.
  • Hi,Anthony.

    I have read Safety Manual(SPNU511D).
    In "7.41 Flash Hard Error Cache and Livelock" describes how Livelock error occur.

    ・Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
    ・ A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload

    I don't know how to above realize it.
    Please tell me how to make this.

    Best Regards.
  • Arriy,

       Here is an example I got to work on a Hercules device.

    Dave2476.SPNU511_7-41_Livelock_Test.zip

  • Hi,David

    Thank you your answer.

    I try to import your project, below error message is indicated.

    " Error:Import failed project 'SPNU511_7-41_Livelock_Test ' because its compiler definition is not available.

    Please install the ARMv15.12 compiler before importing this project - click <'View> CCS App Center' to check if compiler updates are available,

    or install the compiler manually and register it with CCS through 'Preferences > CCS > Build > Compilers'. "

    I can't connect "CCS App Center " in CCS.
    And "ARMv15.12" compiler is not finded.

    What should I do?

  • Arriy,

        Sorry this happens from time to time. There is nothing special about this project you should be able to us it with any version newer than 5x.
        The best thing would be to have the latest version of the compiler installed.

        A procedure for getting the latest compiler from CCS 5 & 6 is open CCS, goto Help, then install new software.
              From the working with menu drop down select all available sites, in the entry box below type "ARM" and enter to filter the options.
              Then select the desired compiler "ARM Compiler Tools 15.x.x", and not just the help for it.

       Another option is to download and install the compiler manually from ti.com, I did a simple google search for ARM compiler site:ti.com and got the following good links.

       Looks like the only the latest version is available for download. Most of the time the latest version will allow you to import the project.

       If importing still does not work another option is to create a new project. 
       Simply delete or backup the existing project files and create a new project SPNA121 is a helpful guide for this.
       Then do a detailed directory compare of the old project files to the new to make sure the only differences are expected such as the compiler version.

       For this example I only changed sys_main.c and sys_link.cmd form the original HALCoGen project.

    Dave

  • HI,Dave.
    Thank you your answer.

    You said "Another option is to download and install the compiler manually from ti.com, I did a simple google search for ARM compiler site:ti.com and got the following good links.".
    But I can't find download page.
    Please tell me address of download page.

    Add question.
    I useing "ARM Compiler Tools 5.2.2".
    If I update to "ARM Compiler Tools 15.x.x" my compiler, will it change significantly?
    If there are changes, what will be changed ?

    Best Regards.
  • Arriy,

    Yes this is a common problem. Please post to the CCS forum.
  • Hi,David.

    I found compiler,and I was able to project imported.

    Even if I run the project you gave me, But Channel 16 of Group 2 of the ESM error flag did not set.

    Is it correct in checking this ESM flag to confirm the error occurrence?

    Is there another way to check the occurrence of Livelock?

  • Arriy,

        There are good comments in the source and yes it includes checking for the expected behavior.

        This project uses flash to generate the livelock which requires it to be programmed as expected which is not the typical usage.
        Typically customers use the default option "Auto generate ECC" but for this we can not because we need to generate multiple single bit errors.

        The project included a compiled flash image which has been verified to work when programmed entirely as expected.
        Please check your settings and make sure the entire image (all sectors main and ECC) are being programmed.
        Because this flash image has expected errors it may be required to disable the verify feature so the programming routine is not interrupted.

        Another behavior of the CPU getting a live lock event is it halting within a few clock cycles of the offending instruction depending on part number.
        This is easy to observe while debugging.

        Another option you could try for this project would be to add an interrupt to grab control of the CPU after the live lock event and continue reporting information.

    Dave

  • Arriy,

    Hope this post will also help.

    e2e.ti.com/.../1408621

    The CPU will retry to read from the TCM memory if it detects a 1-bit error. Normally, this hard error can only happen if the memory has permanent fault. So this is hard to test. I think you can try to create an undefined instruction at the undefined exception vector to cause a livelock event going to the ESM.
  • Thank you your answer.

    I have a question.

     

    "I think you can try to create an undefined instruction at the undefined exception vector to cause a livelock event going to the ESM."

    I can't create undefined instruction in exception vector.

    How do create this ? I am glad that you provide the source code.

  • Below is just one way to generate live lock event. Dave has already shown another way for you.

    In the sys_intvecs.asm change to below for the undefEntry. What I have here is a fmdrr instruction which is VFP instruction.

    resetEntry
            b   _c_int00
    undefEntry
            fmdrr d0,         r1,     r1

    See also below example to create a undefined instruction. I first disable the Vfp and followed by a fmdrr instruction. Since I disable the FPU (Floating Point Unit), any floating instruction will become undefined instructions. When the fmdrr is executed, the CPU will take the exception to the undefEntry at 0x4 which again executes another floating point instruction. This will create a livelock error. See below screenshot in the ESM register. The Stat2 register shows the livelock error.

    int main(void)
    {
    /* USER CODE BEGIN (3) */
    
    	_coreDisableVfp_();
    
    	asm(" fmdrr d0,         r1,     r1");
    
    	while(1);
    /* USER CODE END */
    
        return 0;
    }

  • Hi,Charles.

    Thank you your answer.

    API "_coreDisableVfp _" is undefined in my project.
    Where is _coreDisableVfp_ defined?

    Or please tell me how to disable VFP.

     

    Best Regards.

  • Hi Arriy,

     Sorry, I forgot to tell you that I manually created the _coreDisableVfp _(). See below where I created _coreDisableVfp _ right below _coreEnableVfp_() in the sys_core.asm file.

    ; Enable VFP Unit
    ; SourceId : CORE_SourceId_005
    ; DesignId : CORE_DesignId_006
    ; Requirements: HL_SR492, HL_SR476
    
        .def     _coreEnableVfp_
        .asmfunc
    
    _coreEnableVfp_
    
            mrc   p15,     #0x00,      r0,       c1, c0, #0x02
            orr   r0,      r0,         #0xF00000
            mcr   p15,     #0x00,      r0,       c1, c0, #0x02
            mov   r0,      #0x40000000
            fmxr  fpexc,   r0
            bx    lr
    
        .endasmfunc
    
    ;-------------------------------------------------------------------------------
    ; Disable VFP Unit
    ; SourceId : CORE_SourceId_005
    ; DesignId : CORE_DesignId_006
    ; Requirements: HL_SR492, HL_SR476
    
        .def     _coreDisableVfp_
        .asmfunc
    
    _coreDisableVfp_
    
            mrc   p15,     #0x00,      r0,       c1, c0, #0x02
            orr   r0,      r0,         #0xF00000
            mcr   p15,     #0x00,      r0,       c1, c0, #0x02
            mov   r0,      #0x00000000
            fmxr  fpexc,   r0
            bx    lr
    
        .endasmfunc

  • Hi Charles.

    Thank you your answer.

    Llivelock error occurd in my system too.

    I appreciate to your a lot of teached.

    Best Regards.

  • Hi Arriy,
    Glad your question is answered.
  • Dave, Thanks for posting this. I tried to use it to reproduce Livelock condition on Hercules RM46, no luck. Specifically, the ldr_livelock test reaches the end of the code... I verified in debugger that ldr instruction has 1-bit corrupted, so is the payload, the payload is still being fetched without triggering Livelock. No ESM interrupt, ESM Stat1/2/3 registers remain 0, ErrPinStat stays 1. So, I guess my question is - do you remember any special settings in Code Composer you made to make it work ? E.g. I have to turn off verification in Program/Memory Load options, otherwise I couldn't place ECC segments at 0xf0400000. Anything else ?
  • David, Are there any special Code Composer settings needed to make this work ?
  • The only code composer studio setting I can think of might be the memory map.

    If you have a memory map turned on in CCS then this controls whether it will actually try to read/write the memory you tell it to through the debugger. (think of it as a way to filter out acceeses that may hang the debugger if you are scrolling through memory and come upon an area that were to hang the CPU because it's reserved... )

    So maybe the area you are trying to read/write isn't defined in the memory map?

    See in the CCS Help:

    Code Composer Studio Help > Views and Editors > Control Panel View->Memory Map Overview
  • All,

    Just a side note, you can create an undefined instruction by using the UDF instruction mnemonic,: __asm(" UDF #0");
    This instruction is described in the ARMv7 Architecture Reference Manual and the TI assembler accepts it unlike the UND pseudo-instruction.

    Best Regards,
    Christian