I use TMS570LS3137.
What are the conditions for setting flags ?
I want to know the operation of the system when Livelock occurs.
In order to I execute fault injection test.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I use TMS570LS3137.
What are the conditions for setting flags ?
I want to know the operation of the system when Livelock occurs.
In order to I execute fault injection test.
Hi,Anthony.
Thank you your answer.
When an livelock error actually occurs, I want to exective a failure insertion test in order to ascertain the movement of the system.
Is there no need to perform this failure insertion test ?
Hi Arriy,
We don't have any canned recipe for Livelock creation - it is listed in the SafeTI Diganostic library as something not implemented.
There is a description of the type of ECC error combination that creates a livelock in SPNU511D 7.41 Flash Hard Error Cache and Livelock
So you would need to create this type of ECC error conditon, perhaps using linker generated ECC, to synthesize a livelock.
-Anthony
Hi,Anthony.
I have read Safety Manual(SPNU511D).
In "7.41 Flash Hard Error Cache and Livelock" describes how Livelock error occur.
• Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
• A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload
I don't know how to above realize it.
Please tell me how to make this.
Hi,David
Thank you your answer.
I try to import your project, below error message is indicated.
" Error:Import failed project 'SPNU511_7-41_Livelock_Test ' because its compiler definition is not available.
Please install the ARMv15.12 compiler before importing this project - click <'View> CCS App Center' to check if compiler updates are available,
or install the compiler manually and register it with CCS through 'Preferences > CCS > Build > Compilers'. "
I can't connect "CCS App Center " in CCS.
And "ARMv15.12" compiler is not finded.
What should I do?
Arriy,
Sorry this happens from time to time. There is nothing special about this project you should be able to us it with any version newer than 5x.
The best thing would be to have the latest version of the compiler installed.
A procedure for getting the latest compiler from CCS 5 & 6 is open CCS, goto Help, then install new software.
From the working with menu drop down select all available sites, in the entry box below type "ARM" and enter to filter the options.
Then select the desired compiler "ARM Compiler Tools 15.x.x", and not just the help for it.
Another option is to download and install the compiler manually from ti.com, I did a simple google search for ARM compiler site:ti.com and got the following good links.
Looks like the only the latest version is available for download. Most of the time the latest version will allow you to import the project.
If importing still does not work another option is to create a new project.
Simply delete or backup the existing project files and create a new project SPNA121 is a helpful guide for this.
Then do a detailed directory compare of the old project files to the new to make sure the only differences are expected such as the compiler version.
For this example I only changed sys_main.c and sys_link.cmd form the original HALCoGen project.
Dave
Hi,David.
I found compiler,and I was able to project imported.
Even if I run the project you gave me, But Channel 16 of Group 2 of the ESM error flag did not set.
Is it correct in checking this ESM flag to confirm the error occurrence?
Is there another way to check the occurrence of Livelock?
Arriy,
There are good comments in the source and yes it includes checking for the expected behavior.
This project uses flash to generate the livelock which requires it to be programmed as expected which is not the typical usage.
Typically customers use the default option "Auto generate ECC" but for this we can not because we need to generate multiple single bit errors.
The project included a compiled flash image which has been verified to work when programmed entirely as expected.
Please check your settings and make sure the entire image (all sectors main and ECC) are being programmed.
Because this flash image has expected errors it may be required to disable the verify feature so the programming routine is not interrupted.
Another behavior of the CPU getting a live lock event is it halting within a few clock cycles of the offending instruction depending on part number.
This is easy to observe while debugging.
Another option you could try for this project would be to add an interrupt to grab control of the CPU after the live lock event and continue reporting information.
Dave
Thank you your answer.
I have a question.
"I think you can try to create an undefined instruction at the undefined exception vector to cause a livelock event going to the ESM."
I can't create undefined instruction in exception vector.
How do create this ? I am glad that you provide the source code.
Below is just one way to generate live lock event. Dave has already shown another way for you.
In the sys_intvecs.asm change to below for the undefEntry. What I have here is a fmdrr instruction which is VFP instruction.
resetEntry b _c_int00 undefEntry fmdrr d0, r1, r1
See also below example to create a undefined instruction. I first disable the Vfp and followed by a fmdrr instruction. Since I disable the FPU (Floating Point Unit), any floating instruction will become undefined instructions. When the fmdrr is executed, the CPU will take the exception to the undefEntry at 0x4 which again executes another floating point instruction. This will create a livelock error. See below screenshot in the ESM register. The Stat2 register shows the livelock error.
int main(void) { /* USER CODE BEGIN (3) */ _coreDisableVfp_(); asm(" fmdrr d0, r1, r1"); while(1); /* USER CODE END */ return 0; }
Hi Arriy,
Sorry, I forgot to tell you that I manually created the _coreDisableVfp _(). See below where I created _coreDisableVfp _ right below _coreEnableVfp_() in the sys_core.asm file.
; Enable VFP Unit ; SourceId : CORE_SourceId_005 ; DesignId : CORE_DesignId_006 ; Requirements: HL_SR492, HL_SR476 .def _coreEnableVfp_ .asmfunc _coreEnableVfp_ mrc p15, #0x00, r0, c1, c0, #0x02 orr r0, r0, #0xF00000 mcr p15, #0x00, r0, c1, c0, #0x02 mov r0, #0x40000000 fmxr fpexc, r0 bx lr .endasmfunc ;------------------------------------------------------------------------------- ; Disable VFP Unit ; SourceId : CORE_SourceId_005 ; DesignId : CORE_DesignId_006 ; Requirements: HL_SR492, HL_SR476 .def _coreDisableVfp_ .asmfunc _coreDisableVfp_ mrc p15, #0x00, r0, c1, c0, #0x02 orr r0, r0, #0xF00000 mcr p15, #0x00, r0, c1, c0, #0x02 mov r0, #0x00000000 fmxr fpexc, r0 bx lr .endasmfunc