• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 29 subscribers
  • Views 733 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570 PBIST RAM Groups

Rabie Hammoud
Intellectual 325 points

Hi

i want to run a PBIST at start up on CPU RAM. So the function which start the self-test is as follow: SL_SelfTest_PBIST( PBIST_EXECUTE, CPU RAM, March13).

Which parameter for the CPU RAM should i pass to the function?  I took a look on the TRM (Table 2-5), but i still don't know what is the correct parameter to pass to this function

Could someone please answer this question?

 

 

  • 0
    TI__Guru 65560 points
    The table with the actual mappings of RAM groups to bits is usually in the datasheet not the TRM.
    But, I am not sure which part # you are referring to.

    So if you take the TMS570LS4357 for example, the datasheet is www.ti.com/.../getliterature.tsp and the PBIST RAM groups are listed in Table 6-33. PBIST RAM Grouping on page 105.

    You'll find the same type of table in every datasheet so look in the datasheet for the device in question.

    -Anthony
  • 0 in reply to Anthony F. Seely
    Intellectual 325 points

    Hi

    So this means to run a PBIST on the CPU RAM, i have to exclude all other memories type except the RAM type when i call my function SL_SelfTest_PBIST().

    In the SPNS195C document on page 105 there is Table 6-33 (PBIST RAM Grouping) which maps every memory to its MEM TYPE. So i guess my MEM TYPE which i am looking for (CPU RAM) should be MEM TYPE = 2P.

    is that right?

    Thank you

  • 0 in reply to Rabie Hammoud
    TI__Guru 65560 points
    Rabie,

    You can run PBIST on multiple RAM banks in parallel, so that decision is up to you.

    Regarding CPU RAM and 2P ... in SPNS195C there isn't any CPU RAM in Table 6-33.

    This doc is for the Cortex R5 cache based part with no tightly coupled RAM.

    So your options are R5_ICACHE, R5_DCACHE for the cache memories tied to the CPU and these are all listed as SP,
    and L2RAMW which is level 2 (system level) RAM also SP [SP = single ported memory, not 2P which = two ported memory].