Hi,
I am working on MibSPI with DMA on RM57Lxxx development kit.
I am using MibSPI1 hardware loop back externally shorted MISO and MOSI pins.
I have generated SPI driver using HALCOGEN.
I am unable to trigger the DMA to write tx buffer to mibSPI RAM buffer.I have txbuffer[128] bytes.
My Intialization routines/steps are:
SPI configuration:
1.MIBSPI1 is configured as Master and internally clocked.
2.chip select-0 is used,spi data length-8 bits @ 25Mhz baud rate,.
3.SPI buffer selected 64 buffers which can hold 64 *2 =128 bytes.
4. TG0 is set of this 64 buffer locations. One shot mode and continuous buff mode is used,triger event is selected as always and trigger source is disabled.
5.DMA0CTRL is used to trigger DMA.
SPIDMA channel-0 is mapped to MibSPI[1] to transfer DMA request which is connected to DMAREQ-0 of channel-0 of DMA module
MibSPI[0] to recevie DMA request which is connected to DMAREQ-1 of channel-1 of DMA module.
6. DMA control packets initialization:
void v_dmaSpiTxCtrlPktInit()
{
g_dmaCTRL g_dmaSpi1TxCTRLPKT1;
/*Assign DMA request SCI3 transmit to Channel 0*/
dmaReqAssign(DMA_CH0, DMA_REQ0);
/*Configure control packet for Channel 0 for transmit */
g_dmaSpi1TxCTRLPKT1.SADD = ((uint32_t) (&(spiTxData[0]))); /* source address which is nothing but RAM location */
g_dmaSpi1TxCTRLPKT1.DADD =(uint32) (&(pMibSpi1Ram->tx[0].data)); /* destination address which is nothing but Buffer register */
g_dmaSpi1TxCTRLPKT1.RDSIZE = ACCESS_64_BIT; /* read size */
g_dmaSpi1TxCTRLPKT1.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaSpi1TxCTRLPKT1.CHCTRL = 0; /* channel control */
g_dmaSpi1TxCTRLPKT1.FRCNT = 1U; /* frame count */
g_dmaSpi1TxCTRLPKT1.ELCNT = (sizeof(spiTxData) / sizeof(spiTxData[0])) / 4; ; /* element count */
g_dmaSpi1TxCTRLPKT1.ELDOFFSET = 4U; /* element destination offset which is nothing but Buffer register */
g_dmaSpi1TxCTRLPKT1.ELSOFFSET = 1U; /* element Source offset which is nothing but RAM location */
g_dmaSpi1TxCTRLPKT1.FRDOFFSET = 0U; /* frame destination offset */
g_dmaSpi1TxCTRLPKT1.FRSOFFSET = 0U; /* frame Source offset */
g_dmaSpi1TxCTRLPKT1.PORTASGN = PORTA_READ_PORTB_WRITE; //Data RAM to SPI RAM register
g_dmaSpi1TxCTRLPKT1.TTYPE = FRAME_TRANSFER; /* transfer type */
g_dmaSpi1TxCTRLPKT1.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaSpi1TxCTRLPKT1.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaSpi1TxCTRLPKT1.AUTOINIT = AUTOINIT_OFF; /* autoinit */
/*Set control packet for channel 0 */
dmaSetCtrlPacket(DMA_CH0, g_dmaSpi1TxCTRLPKT1);
/*Set dma channel 0 trigger on hardware request*/
dmaSetChEnable(DMA_CH0, DMA_HW);
}
//void v_dmaSpiRxCtrlPktInit(uint16 *u8_receiBuffer)
void v_dmaSpiRxCtrlPktInit()
{
g_dmaCTRL g_dmaSpi1RxCTRLPKT2;
/*Assign DMA request SCI3 transmit to Channel 0*/
dmaReqAssign(DMA_CH1, DMA_REQ1);
/*Configure control packet for Channel 1*/
g_dmaSpi1RxCTRLPKT2.SADD = (uint32)&(pMibSpi1Ram->rx[0].data); /* source address which is nothing but RAM location */
g_dmaSpi1RxCTRLPKT2.DADD = ((uint32) (&(spiRxData[0]))); /* destination address which is nothing but RAM location*/
g_dmaSpi1RxCTRLPKT2.CHCTRL = 0; /* channel control */
g_dmaSpi1RxCTRLPKT2.FRCNT = (sizeof(spiRxData) / sizeof(spiRxData[0])) / 4; /* frame count */
g_dmaSpi1RxCTRLPKT2.ELCNT =4U; /* element count */
g_dmaSpi1RxCTRLPKT2.ELDOFFSET = 1ul << g_dmaSpi1RxCTRLPKT2.WRSIZE;/* element destination offset */
g_dmaSpi1RxCTRLPKT2.ELSOFFSET = 2ul << g_dmaSpi1RxCTRLPKT2.RDSIZE; /* element Source offset */
g_dmaSpi1RxCTRLPKT2.FRDOFFSET =4ul << g_dmaSpi1RxCTRLPKT2.WRSIZE; /* frame destination offset */
g_dmaSpi1RxCTRLPKT2.FRSOFFSET = 0ul << g_dmaSpi1RxCTRLPKT2.RDSIZE; /* frame source offset */
g_dmaSpi1RxCTRLPKT2.PORTASGN = 4ul; //PORTB_READ_PORTA_WRITE;
g_dmaSpi1RxCTRLPKT2.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaSpi1RxCTRLPKT2.WRSIZE = ACCESS_64_BIT; /* write size */
g_dmaSpi1RxCTRLPKT2.TTYPE = FRAME_TRANSFER; /* transfer type */
g_dmaSpi1RxCTRLPKT2.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaSpi1RxCTRLPKT2.ADDMODEWR = ADDR_INC1; //ADDR_INC1; /* address mode write */
g_dmaSpi1RxCTRLPKT2.AUTOINIT = AUTOINIT_OFF; /* autoinit */
/*Set control packet for channel 1*/
dmaSetCtrlPacket(DMA_CH1, g_dmaSpi1RxCTRLPKT2);
/*Set dma channel 0 trigger on hardware request*/
dmaSetChEnable(DMA_CH1, DMA_HW);
}
Request you to please help where I am doing mistake in trigger dma to transfer 128 byes of data to mibSPI TX RAM