CCS/RM48L950: What is the relationship between EMIF and MPU?

clark jam

Part Number: RM48L950
Other Parts Discussed in Thread: HALCOGEN,

Tool/software: Code Composer Studio

Hello:
I have a question to need your help.
I use EMIF asynchronous interface CS2 to connnect with external SRAM, in the case of EMIF is configured correctly, the entire SRAM space to first write then read and then compare read and write data, found that individual address data inconsistencies. If before reading and writing, first call HALCoGen generated _mpuInit_ () and _mpuEnable_ () function to initialize and enable the MPU, and then the entire space to first write then read and then comparison, the data exactly the same. why? What is the relationship between EMIF and MPU?
Best regards,

over 7 years ago

0 Bob Crosby over 7 years ago

TI__Guru 72500 points

I suspect the problem you are seeing is related to advisory EMIF#4. The MPU may be changing the EMIF space from "Normal" to "Device" or "Strongly Ordered" and avoiding this problem.

This is from SPNZ223B page 37.

0 Bob Crosby over 7 years ago in reply to Bob Crosby

TI__Guru 72500 points

0 clark jam over 7 years ago in reply to Bob Crosby

Prodigy 160 points

Dear Bob Crosby:
Thanks for your helps, I see the relationship between EMIF and MPU. but now, TCPIP protocol stack runs normally in the internal RAM of RM48L950 chip, I move TCPIP protocol to external SRAM, it runs abnormally. Can you tell me the different point between internal RAM and external SRAM. I need your help.
Best regards

0 Bob Crosby over 7 years ago in reply to clark jam

TI__Guru 72500 points

Access to an external SRAM will be much slower than access to internal RAM, but I am not sure why that would affect your TCPIP protocol stack.

0 clark jam over 7 years ago in reply to Bob Crosby

Prodigy 160 points

Dear Bob Crosby:
when I access to an external sram， you tell me: I need to configure device type from "normal" to "strongly ordered" using the CPU's MPU. so I use _mpuInit_ () and _mpuEnable_ () function to initialize and enable the MPU in the sys_startup.c source file. but I use SafeRTOS Operation system, the OS may cover my external sram region's type, how to change default region type set?
I need your help.
Best Regards,
Clark.

0 Bob Crosby over 7 years ago in reply to clark jam

TI__Guru 72500 points

You can use CCS to see how the MPU regions are configured. Expand Cp15 in the register tab.

0 clark jam over 7 years ago in reply to Bob Crosby

Prodigy 160 points

Dear Bob Crosby:
Thanks for you help. You said "use CCS to see how the MPU regions are configured. Expand Cp15 in the register tab", If I want to know the MPU area is configured, how to know whether the MPU area is configured successfully? That is, where to view the MPU regional configuration results? For example: how to check / confirm EMIF has been working in the "strongly ordered" type?
I need your help.
Best regards

0 Bob Crosby over 7 years ago in reply to clark jam

TI__Guru 72500 points

There are 15 sets of MPU regions. In the case of overlapping areas, the higher number region has priority. I suggest start with region 15 by setting the "CPU_MPU_REGION_NUMBER" register highlighted above to 0xF. Then look at the BASE_ADDRESS and REGION_SIZE_ENABLE registers to see if that region covers the address space in which you are interested. If not, decrease the "CPU_MPU_REGION_NUMBER" register and check again. The description of these registers is in the ARM Cortex R4 TRM section 4.2.19.

0 clark jam over 7 years ago in reply to Bob Crosby

Prodigy 160 points

Dear Bob Crosby:
Thanks for you help. I can find Cp15 register groups in CCS IDE, but I can't find Cp15 register groups In IAR IDE. now, I use IAR as IDE, can you tell me how to look at Cp15 register groups in IAR IDE?
Best Regards,

0 Bob Crosby over 7 years ago in reply to clark jam

TI__Guru 72500 points

Sorry, I do not have any experience with the IAR debugger. Perhaps someone else on the forum can help you. You may have to pose that question to IAR.
Have you looked to see how the regions were configured in HALCoGen?

0 clark jam over 7 years ago in reply to Bob Crosby

Prodigy 160 points

I had looked to see how the regions were configured in halcogen. but I don't konw where to look at all regions set result.

Thanks for your helps.

Bests regards!

0 Bob Crosby over 7 years ago in reply to Bob Crosby

TI__Guru 72500 points

Look under the "RM48L950" tab for the "R4-MPU-PMU" sub tab.

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CCS/RM48L950: What is the relationship between EMIF and MPU?