TMS570LC4357: implementing variable switching frequency without resolver encoder

Hi user4313736 ,

Sounds like a very interesting problem..

But I can't tell where the questions are exactly.
- how to implement a variable frequency PWM
- how to synchronize ADC conversions w. the PWM

And I don't really have a clear idea of the set of constraints for each of these problems.

We haven't developed any R2D converter application notes w. Hercules. But we can assist with the
individual elements of the problem if you want to discuss further.

Best Regards,
-Anthony

Hi Anthony,

Yes, it´s an interesting problem indeed.

To implement a variable frequency PWM is not so difficult, that´s not an issue. How to synchronize ADC conversions w. the PWM signals is. It all boils down to this:

Pre-requisite 1:
One fixed frequency PWM resolver exitation signal is generated. The ADC sampling of the resulting resolver position signals sin and cos must be synchronized with the PWM signal, i.e. the ADC sampling is triggered from the PWM module. It is acceptable to sample the sin and cos signals in sequence after each other with 1us in between them, but ideally they should be sampled at the exact same time, which requires use of both ADCs.

Pre-requisite 2:
Six PWM signals controlling the motor are generated. They are complements of each other in pairs, so only three PWM modules are needed to generate the six signals. The three PWM modules are synchronized with each other. The ADC sampling of the motor currents and voltage must be synchronized with the PWM signals, i.e. the ADC sampling is triggered from the PWM module. Two of the currents have to be sampled at exactly the same time, which requires using both ADC:s. The third current and the voltage must be sampled close (in the range of 1us) to this time. The PWM frequency of the PWM signals is continuously variable.

Problem:
The ADC sampling must be synchronized with both a fixed frequency PWM and a continuously variable frequency PWM. This means that the sampling will sometimes overlap and sometimes not. At least one sampling requires the use of both the ADCs. How can the ADC sampling be coordinated in a good way?


Does this make the problem and constraints clearer?

Best regards

Hi user4313736 ,

I think it's clear now, the question is more of a 'what to do' though rather than a 'how to do'.. And for that reason I'm not sure we can be helpful.

If I understand, in the ideal case you would like 5 independent Sample & Hold circuits for this system:

2 - for Sin/Cos signals of the resolver
3 - for PWM phase currents

And you've identified compromises to make that can get you to 2 S/H:

1 - for Sin/Cos, by measuring them back to back within 1us
2 - for the PWM phase currents, measuring 2 simultaneously and the third immediately after

But that gets you to 3 S/H and you only have 2 S/H on the device.

So you can either add an external ADC, or make 1 more compromise ..

Identifying the 1 more compromise isn't something we really have the expertise to help with here. I think to answer this question you need the expert in the control systems domain. I think you're needing an analysis of the 'Angle Tracking Observer' .. whatever is taking the RAW samples from the Sin/Cos outputs of the resolver and converting these to an angle estimate .. to help nail down what is the impact of introducing yet another us or two of delay (or lead) on the sample times of the signals feeding this observer. Similar analysis might be needed in understanding the impact if you move the phase current measurement. With nonlinear feedback involved here I wouldn't even hazard a guess. It *does* sound like an interesting problem and someone(s) probably written papers about the tradeoffs .. that might be a place to start.

Once you figure out the strategy - we can help w. the implementation on the MCU but to be honest even though the ADC has the ability to prioritize one set of conversions over another, this is only really relevant when they are triggered at the same time. Even if you prioritize the one over the other, if the lower priority conversion starts slightly before (say 30ns) the higher one, it will complete and you'll still get an uncertainty in the sample time of the high priority channel.

The only thing I can suggest now is to also consider running the ADCs in a continual conversion mode dumping their results to a circular buffer. Maybe it's doing: SIN + Phase 1, Cos + Phase 2, Phase 3, Sin+Phase1... etc.
over and over on the 2 ADCs. Then at least you could dump these into an array in memory and using index pull out the samples that are 'closest' in time to where you would ideally pull from, and you would also know exactly what the delta-T error is so that you may get a better result correcting for this (rather than trying to correct when you *don't* know the delta-T error due to slight variations in order introduced by PWM->ADC trigger relative delays...)

Good luck w. this problem it does sound very meaty.

Best Regards,
Anthony

Hi Anthony,

Thank you very much for your answer! This kind of answer was exactly what I was looking for.

From this I conclude the following:
- There are no application examples or similar that you (TI) has issued, or know of, which could help with this specific problem.
- We haven´t overlooked anything obvious; this is hard to solve with our current setup.
- The best thing in the long run would probably be to add a resolver encoder.

The possible compromises you suggest are in essence equal to the ones I´m currently considering. I´m currently discussing the drawbacks of these with our experts in the control systems domain, just as you suggest, to see what compromise, if any, that can be acceptable.

Thank you for the fast and competent support!

Best regards

Hi user4313736 ,

Super glad this helped even if the answer isn't there.

Correct - we don't have any application examples *for Hercules* products that address this issue.

There may be some expertise on this topic on the C2000 E2E forum: e2e.ti.com/.../

I think that team does provide code for an implementation of an ATO and most of the digital controls expertise in TI is concentrated in that team, so you *might* be able to get another opinion on the topic by posting there.

I would just make it clear in the post (if you decide to) that:
a) the problem is for a Hercules device with only 2 S/H
b) please do not move the post back to the Hercules forum. You are looking for guidance/advice from some of the
control experts in C2000 not a specific implementation answer for Hercules.

I'm afraid if you don't put (b) the post will just get moved to this forum.
And I believe the C2000 devices include extra S/H circuits for simultaneous sampling (even though the conversions are serialized)
so they don't have exactly the same limitations as Hercules does.

Best Regards,
-Anthony

Hi user4313736,

Please note, that TI has a nice integrated solution for a resolver encoder the PGA411-Q1 and that this device is also part of SafeTI-26262.

Best Regards,
Christian

Hi Christian,

Very interesting, thank you.

Best regards