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TMS570LS0714: Leakage Currents and Conditions

Alex Segler
Expert 4261 points
Part Number: TMS570LS0714

Hello all,

Table 7-24 in the TMS570LS0714 datasheet lists the leakage currents for the device in on-state:

  • Is this only when the ADC is connected and sampling, and if so what is the off-state input bias current

OR

  • Is this continuous leakage per input pin when the ADC peripheral is turned on?

How are these values measured? By design? What are the statistics of these i.e. is this 3 sigma? 1 sigma? Are these a function of temperature, process, voltage?

Also - when the ADC is doing a conversion is the stated input current what it takes to charge the mux capacitors + sampling capacitor + current called out in 7-24 or does 7-24 take the mux and sampling capacitors into account? We have some high impedance sources driving the ADC – let’s say 3.3k resistor. If there is a leakage current that is called out in table 7-24, we will see 40LSBs of error due to the leakage current and one way to fix this is to add voltage followers/buffers and that is not reasonable in our design.

Thank you in advance!

 

  • 0
    TI__Guru 59540 points

    Hello Alex:

    The content of the table is:

    • Is this only when the ADC is connected and sampling, and if so what is the off-state input bias current

    OR

    • Is this continuous leakage per input pin when the ADC peripheral is turned on?

    As noted in the table, it is the off state leakage. Off state bias is the same as off state leakage.

    These values are derived through characterization across process, voltage, and temperature with a targeted cpK of 2.

    In regard to your last question, you may want to have a look at these application notes:

  • 0 in reply to Chuck Davenport
    Prodigy 35 points
    Thank you for the references; we had looked at them before asking Alex but unfortunately, they don't answer the question.

    Iadsb1, Iadsb2 are labeled: ADC[1|2] Analog on-state input bias current and they are bounded values. Looking at Figure 7 of SPNA140, there is a 250 ohm Rmux followed by a Cmux of 16pF - let's ignore the rest of the network for a minute.

    Let's say the AD IN is 3.3V, Cmux is discharged and we close the Mux switch. This means the current coming in from AD IN will be 3.3V / 250ohm = 13.2mA. This is much higher than the input bias current - so this can't be the input bias current. Yes? I believe the two references above, address this particular current.

    When I read "bias current", I think no matter what else you do, you have to source/sink this to get the input to work.

    The problem we are trying to work out is, if Iadsb[1|2] are indeed the input bias currents, then this is not a good ADC. The reason is as follows.

    Let's say we have a source impedance of 1k Ohms. An input bias current range of -8uA to 10uA will cause 800mV (=1k * 8uA) to 1000mV (=1k * 10uA) of offset which is 10LSBs to 12LSBs of error assuming a 3.3V Vref and a 12 bit conversion.

    With higher source impedances, the error due to input bias current gets to be even worse. In the original question, at 3.3k source impedance, we get 40LSBs of error.
  • 0 in reply to Harjit Singh
    TI__Guru 59540 points
    Hello Harjit,

    I've reached out to our ADC expert in order to address your comments/concerns. We will get back to you soon.
  • 0 in reply to Harjit Singh
    TI__Guru 59540 points

    Hello Harjit,

    Below is the reply from our ADC expert

    "..., the resulting 10-12LSB error calculation is correct, as is their understanding of bias current. And yes, the higher the source resistance, the higher the bias current error."

    Can you provide more detail about what you are trying to measure so that we could see if there are methods that can be used to provide more accurate measurements?

  • 0 in reply to Chuck Davenport
    Prodigy 35 points

    We have sensors that have an RC anti-aliasing filter that has a source impedance of 3k to 5k followed by a capacitor. At 3.3k source impedance, we have 40LSBs to 50LSBs of error. Doing a ratiometric scaling, at 5k, we will have 67LSBs to 83LSBs of error.

    I would like more information on why there is such a large input bias current, how it varies with process, voltage and temperature.

    Thank you.

  • 0 in reply to Harjit Singh
    TI__Guru 59540 points
    Hello Harjit,

    Below is the response from our ADC expert.

    "Min and max numbers in the data sheet are set under absolute worst-case PVT conditions. Input bias currents vary by orders in magnitude with process, voltage and temperature. An order in magnitude change with voltage can be seen in data sheet numbers. Other customers ensure their inputs stay within the VSSAD + 100 mV < Vin < VCCAD – 200 mV to avoid sharp spikes up at Vin = VCCAD and sharp spikes down at Vin = VSSAD. Temperature has the strongest impact as input bias current is the result of accumulated leakage paths."

    If there are remaining questions or concerns, let me know and we can set up a call between all interested parties to close this discussion more quickly.
  • 0 in reply to Chuck Davenport
    Prodigy 35 points

    I would like a call, please. How do we set it up?

  • 0 in reply to Harjit Singh
    TI__Guru 59540 points
    Hello Harjit,

    Do you have a local TI office and/or TI representative that you are working with? If so can help to coordinate a call and as your direct support, would be ideal to have engaged in the discussion.

    Otherwise, I will reach out to you with the messaging feature of this forum so we can exchange contact details that can be used to setup a call/webex as necessary.
  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points
    Alex/Harjit,

    I am closing this thread since it was handled off line and is now taken care of. If there is a need for additional discussion, a new post to this thread will reopen it.