Other Parts Discussed in Thread: HALCOGEN
Hello,
I used an SCI-DMA (example_sci_dma.c) example from HALCoGen version 04.06.00.
With changes described in e2e.ti.com/group/launchyourdesign/m/boosterpackcontest/666341 it passes (all bytes have been sent, received and accounted for), however I was surprised to see the values in the Working Control Packet registers:
TX: PCP ISADDR=0x807f000 IDADDR=0xfff7e53b ITCOUNT=0x400001 CHCTRL=0x8
WCP CSADDR=0x807f03f CDADDR=0xfff7e53b CTCOUNT=0x10001
RX: PCP ISADDR=0xfff7e537 IDADDR=0x807f040 ITCOUNT=0x400001 CHCTRL=0x2
WCP CSADDR=0xfff7e537 CDADDR=0x807f07e CTCOUNT=0x20001
The register values were obtained by the following code placed after printf("Pass\n"):
printf("TX: PCP ISADDR=0x%x IDADDR=0x%x ITCOUNT=0x%x CHCTRL=0x%x\n", dmaRAMREG->PCP[DMA_CH0].ISADDR, dmaRAMREG->PCP[DMA_CH0].IDADDR, dmaRAMREG->PCP[DMA_CH0].ITCOUNT, dmaRAMREG->PCP[DMA_CH0].CHCTRL);
printf(" WCP CSADDR=0x%x CDADDR=0x%x CTCOUNT=0x%x\n", dmaRAMREG->WCP[DMA_CH0].CSADDR, dmaRAMREG->WCP[DMA_CH0].CDADDR, dmaRAMREG->WCP[DMA_CH0].CTCOUNT);
printf("RX: PCP ISADDR=0x%x IDADDR=0x%x ITCOUNT=0x%x CHCTRL=0x%x\n", dmaRAMREG->PCP[DMA_CH1].ISADDR, dmaRAMREG->PCP[DMA_CH1].IDADDR, dmaRAMREG->PCP[DMA_CH1].ITCOUNT, dmaRAMREG->PCP[DMA_CH1].CHCTRL);
printf(" WCP CSADDR=0x%x CDADDR=0x%x CTCOUNT=0x%x\n", dmaRAMREG->WCP[DMA_CH1].CSADDR, dmaRAMREG->WCP[DMA_CH1].CDADDR, dmaRAMREG->WCP[DMA_CH1].CTCOUNT);
I have a few questions:
1) Why the transmit Current Transfer Count Register (CTCOUNT) value shows that the current remaining frame counts and the current remaining element counts are 1 (I expected 0) and the Current Source Address Register (CSADDR) points to the last byte address?
2) Why the receive Current Transfer Count Register (CTCOUNT) value shows that the current remaining frame counts is 2 (I expected 0) and the current remaining element counts is 1 (I expected 0) and the Current Destination Address Register (CDADDR) points to the last 2 bytes address?
3) (The most important) How can I obtain the real number of bytes received or the address of the last byte transfered by the DMA (alternatively the address, where the next received byte would be placed), without knowledge of number of bytes sent?
