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TMS570LC4357: Cortex-R5 system validation registers in TM570LC

Etienne Alepins
Intellectual 775 points
Part Number: TMS570LC4357

Hi,

1) TMS570LC4357 uses the Cortex-R5F. ARM's Cortex-R5F TRM (DDI0460D)  describes in "§4.1.6 System validation" registers such as "nVAL IRQ Enable Set Register", "nVAL FIQ Enable Set Register" and "nVAL Reset Enable Set Register" which allow to trigger an IRQ, FIQ or reset to the CPU through raising the nVALIRQm, nVALFIQm and nVALRESETm signals. We plan to set the PMU's PMUSERENR.EN bit to true, thus allowing User mode to read/write to every System Validation registers and almost every PMU registers. However, we want to make know to what extend User code could impact the system by using the System Validation registers.

We've found no documentation from TI telling how the nVALIRQm, nVALFIQm and nVALRESETm signals and handled in the TMS570LC. Are they routed? What is their effect? Is it possible to disable their effects?

Initially, we thought that nVALIRQm and nVALFIQm would simply raise an interrupt at the VIM through the VIM channel 22 ("Cortex-R5F PMU Interrupt"). However, this is the channel used for PMU interrupt, so we now doubt that System Validation interrupts are also signaled through this channel.

2) We also have a second question regarding PMU interrupts raised by configuring PMINTENSET register. When the interrupt is raised by the core, nPMUIRQm signal is set. Where is this signal used in the TMS570LC? The TMS570LC Datasheet rev C shows the nPMUIRQm signal in "§6.22.3 Embedded Cross Trigger". How does the PMU interact with the CTI? Also, is nPMUIRQm also routed elsewhere than to the CTI?

Thanks.

  • 0
    TI__Guru 59540 points
    Hello Etienne,

    For sure, there are often optional features that are left up to the core integrator to decide how they hook them up or even if they are included in the RTL synthesis of the R5F Core. For these specific features, I am not certain how they were handled. I need to check with our device architect and possibly the design team to confirm the validation register handling. Note that this may take a few days given holiday schedules and time zone differences.

    In regard to the PMUINTREQ hook up, I will also need to do some investigation and get back with you. Again, this may take a few days since our LC43xx device expert is currently out of the office on holiday.

    My apologies in advance for the delays.
  • 0 in reply to Chuck Davenport
    Expert 1020 points

    Hi,

    Thanks Chuck. Do you have any news on the subject?

    Best regards,

    Gael

  • 0 in reply to Gael Le Moing
    TI__Guru 59540 points
    Hello Gael,

    I am still waiting on news from our designers on this. Apologies for the delay.
  • 0 in reply to Chuck Davenport
    TI__Genius 11645 points
    Hello Gael, Etienne,

    Apologies for the delay.

    Going back to your questions,

    #1)
    Like chuck mentioned above, these signals are optional and left to the core integrator. In our design all the three signals(nVALIRQm, nVALFIQm and nVALRESETm) are left open and will not have any effect of the system.

    #2)
    nPMUIRQm signal gets routed to both the VIM(Interrupt) module as well as CTI. Both are handled independent of each other.
    You can refer to the following section of the datasheet, 6.15.3 Interrupt Request Assignments (VIM Interrupt Channel 22).

    Hope that helps !
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Expert 1020 points

    Hello Karthik,

    Thank you for the answers.

    The signal "VALEDBGRQm" is also in the list of the validation signals (Appendix A.12 of the Cortex-R5f TRM): is this one also not routed in the TMS570LC4357?

    Best regards,

    Gael

  • 0 in reply to Gael Le Moing
    TI__Genius 11645 points
    That's correct. VALEDBGRQm is also left open and will not have any effect on the system.
  • 0 in reply to KARTHIKEYAN RAJAMANICKAM
    Intellectual 775 points

    1) That means the whole "Validation Registers" feature of the Cortex-R5 core is not usable in the TMS570LC, right? It is not normal not to find this information in TI's documentation. Could the RM or Datasheet be updated to indicate all Validation Registers have no effect in the TMS570LC or to write individually that each discussed signals are not connected?

    However, there is still the "c15, Cache Size Override Register" which might or might not be usable. Please make sure the documentation update you'll perform also cover this register. In our case, it is only accessible in Privileged mode, so we don't care.

    2) Thanks for the confirmation about the nPMUIRQm. However, we do not really understand the role and behavior of the CTI. Which document should we read to understand what effect nPMUIRQm has on the whole TMS570LC through the CTI?

    Thanks.

  • 0 in reply to Etienne Alepins
    TI__Guru 59540 points

    Hello Etienne,

    Sorry for the delay in replay as I was out of the office on Holiday.

    Etienne Alepins said:
    1) That means the whole "Validation Registers" feature of the Cortex-R5 core is not usable in the TMS570LC, right?

    Based on Kartik's response, that is correct.

    Etienne Alepins said:
    It is not normal not to find this information in TI's documentation. Could the RM or Datasheet be updated to indicate all Validation Registers have no effect in the TMS570LC or to write individually that each discussed signals are not connected?

    It is normal for us to not include details regarding CPU related registers in our documentation. Validation Registers as you have indicated are also not included in our documentation. We rely on the ARM documentation to discuss/document ARM specific functionality. I understand that this is a bit different in that it is a register set specifically for validation that was not hooked up so there is an opportunity to improve the documentation regarding CPU hookup within the system. I don't know if there is any ARM documentation included in their TRM regarding the options for including this or not, but certainly, if it is not hooked up it will not impact device operation within an active application.

    Etienne Alepins said:
    However, there is still the "c15, Cache Size Override Register" which might or might not be usable. Please make sure the documentation update you'll perform also cover this register. In our case, it is only accessible in Privileged mode, so we don't care.

    Although there are plans for documentation updates for corrections, clarifications, and such, there are no plans for major updates to content. However, I will notify our documentation team of your concerns so it can be considered.

    Etienne Alepins said:
    2) Thanks for the confirmation about the nPMUIRQm. However, we do not really understand the role and behavior of the CTI. Which document should we read to understand what effect nPMUIRQm has on the whole TMS570LC through the CTI?

    Please provide more specific information on what you need for the CTI. I believe there is more information on the CTI within the Debug Architecture Documents from ARM. Again, this is ARM IP so your best source of answers on this might be to ask ARM but we will do our best to address specific concerns or questions.

  • 0 in reply to Chuck Davenport
    Intellectual 775 points
    I agree TI should not repeat in its documents the information found in ARM documents. However, this question is about how the ARM core has been _integrated_ in TI TMS570LC SoC, a question to which the answer should obviously be written in TI docs.

    2) Yes, but I am a bit confused in all ARM documents... Is the following document the one being applicable to the TMS570LC for CTI description: CoreSight SoC TRM (DDI0480C)?

    Thanks!
  • 0 in reply to Etienne Alepins
    TI__Guru 59540 points

    Hello Etienne,

    Etienne Alepins said:
    I agree TI should not repeat in its documents the information found in ARM documents. However, this question is about how the ARM core has been _integrated_ in TI TMS570LC SoC, a question to which the answer should obviously be written in TI docs.

    I understand your point here and can only state that this has not been the common practice from TI for quite some time. I do not know the history of why this is so, but can only state that the current approach of not listing out the CPU specific implementation details has been common practice for many years and there are no plans to change this approach.

    Etienne Alepins said:
    2) Yes, but I am a bit confused in all ARM documents... Is the following document the one being applicable to the TMS570LC for CTI description: CoreSight SoC TRM (DDI0480C)?

    Yes, this is the correct document to reference for the CTI implemented in the LC43xx Hercules device.