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TMS570LC4357: EMIF SDRAM controller operation details

Part Number: TMS570LC4357

Hello,

I am looking for more details on the exact behavior of the SDRAM controller of the EMIF. 

In particular, I would like to understand if really all read/write accesses start with an ACT command, or if the memory controller is first checking if the row/bank is already open and then proceeds to the read/write operation skipping the ACT. 

Also it's not clear to me when an open row is closed since auto precharge is not used. 

Any information will be appreciated. 

Mathieu

  • Hello Mathieu,

    I have posed this question to one of our EMIF experts for further clarification and details. They are currently out of the office, but I am hopeful they will be able to provide an answer to me tomorrow (Friday). My apologies for the delay.

    Thanks and Regards,

    Chuck Davenport

  • Hello Mathieu,

    My apologies for the delayed response as I had to touch base with our design support personnel to get a definitive answer on the internal workings of the EMIF.

    The EMIF does not always issue an ACT command before a read/write. The EMIF maintains a list of open row/banks. If the row/bank for a read/write command is open, the EMIF executes read/write without issuing an ACT command. If a row other than that required by the read/write is open, the EMIF will issue a PRECHARGE command to close the open row in that bank followed by an ACT command to open the required row, followed by the read/write.

    The EMIF does not implement auto-precharge. The EMIF will close row in a bank only when a different row in the same bank is required by a command. It also closes all row/banks before issuing refreshes, before low-power mode entry such as self-refresh, or if tRAS_max timer expires.

    Thanks and Regards,

    Chuck Davenport

  • In reply to Chuck Davenport:

    Makes sense.
    Many thanks for the detailed and complete answer.

    Mathieu
  • In reply to Chuck Davenport:

    Hello,

    As a follow up question, I would like to know if a read burst can be interrupted by a write command. This case is not listed in the TRM, but it seems strange to me. 

    In case a read burst can be interrupted by a write, I would like to know if the DQM signals are used to start the bus turnaround. 

    Best regards,

    Mathieu

  • In reply to Mathieu Patte:

    Hello,

    Would it be possible to have an answer on this point ? 

    Best,

    Mathieu

  • In reply to Mathieu Patte:

    Hello Mathieu,

    Again, I need to go back to the designer to get a response on the inner workings. I will do so and get back with you. Apologies for the delay.

    Thanks and Regards,

    Chuck Davenport

  • In reply to Chuck Davenport:

    Thanks, I just wanted to make sure that this thread was till active. 

  • In reply to Mathieu Patte:

    Hi Mathieu,

    I am still waiting to hear back from our experts. Sorry for the extended delay.

    Thanks and Regards,

    Chuck Davenport

  • In reply to Chuck Davenport:

    Hi,

    Thanks for keeping me posted. I shall wait! 

    Mathieu

  • In reply to Mathieu Patte:

    Mathieu,

    The explanation from our IP expert is that the EMIF does support termination/interruption of a Write burst with a Read command. It will always use a Burst Terminate Command to interrupt/terminate any ongoing read/write burst.

    Thanks and Regards,

    Chuck Davenport