Other Parts Discussed in Thread: TMS570LS1224
I am currently implementing run time checks of SafeTI (same tests works during start-up).
All FEE tests works ok (including fault injections), so I moved to SRAM tests and immediately received error. SRAM_PAR_ADDR_CTRL_SELF_TEST test is causing problems.
SL_SelfTest_SRAM() returns ST_FAIL in SL_SelfTest_Result* sram_stResult
Reason for failure is this check (RAM write part)
if ((TCRAM_RAMERRSTAT_WADDRPAR_FAIL == (uint32)(sl_tcram1REG->RAMERRSTATUS & TCRAM_RAMERRSTAT_WADDRPAR_FAIL)) && /* Write parity error on B1 */
(TCRAM_RAMERRSTAT_WADDRPAR_FAIL == (uint32)(sl_tcram2REG->RAMERRSTATUS & TCRAM_RAMERRSTAT_WADDRPAR_FAIL)) && /* Write parity error on B2 */
(0 != (sl_esmREG->SSR2 & ((uint32)1U << ESM_G2ERR_B0TCM_ADDPAR))) && /* B1 Parity error */
(0 != (sl_esmREG->SSR2 & ((uint32)1U << ESM_G2ERR_B1TCM_ADDPAR)))) { /* B2 parity error */
*sram_stResult = ST_PASS;
} else {
*sram_stResult = ST_FAIL;
}
And there it is that sl_tcram2REG check, I have value 0x100 in status and 0x200 is expected.
From this line
sramEccTestBuff[0] = 0xAAAAAAAABBBBBBBBUL; /* Generate write parity error on B1 & B2 */
code jumps to ESM interrupt handler (sl_esm_high_intr_handler()) and when this line line is reached (cpu registers pushed to stack (which is in RAM) the 0x100 is already present in tcram2 status.
esmOffH = (uint8)sl_esmREG->IOFFHR;
So most likely it looks like that this test is not meant to be run while FIQ interrupts are enabled, so this test cannot be run during runtime of the SW.
I double tested the findings by inserting the register printing just before checking the register content (should be safe here based on the comments in lines before that)
/* Restore parity, so that we can use the stack */
/*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
sl_tcram1REG->RAMCTRL = (sl_tcram1REG->RAMCTRL & 0xF0FFFFFFU);
/*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
sl_tcram2REG->RAMCTRL = (sl_tcram2REG->RAMCTRL & 0xF0FFFFFFU);
DBG_PRINT( "TCRAM1_STAT: 0x%x, TCRAM2_STAT: 0x%x\r\n", sl_tcram1REG->RAMERRSTATUS, sl_tcram2REG->RAMERRSTATUS );
if ((TCRAM_RAMERRSTAT_WADDRPAR_FAIL == (uint32)(sl_tcram1REG->RAMERRSTATUS & TCRAM_RAMERRSTAT_WADDRPAR_FAIL)) && /* Write parity error on B1 */
(TCRAM_RAMERRSTAT_WADDRPAR_FAIL == (uint32)(sl_tcram2REG->RAMERRSTATUS & TCRAM_RAMERRSTAT_WADDRPAR_FAIL)) && /* Write parity error on B2 */
(0 != (sl_esmREG->SSR2 & ((uint32)1U << ESM_G2ERR_B0TCM_ADDPAR))) && /* B1 Parity error */
(0 != (sl_esmREG->SSR2 & ((uint32)1U << ESM_G2ERR_B1TCM_ADDPAR)))) { /* B2 parity error */
*sram_stResult = ST_PASS;
} else {
*sram_stResult = ST_FAIL;
}
And the results shows same as check via debugger...
TCRAM1_STAT: 0x200, TCRAM2_STAT: 0x100<CR><LF>
Tried also printing after if-sentence and result is same...
There is no mentions anywhere that this test cannot be run while FIQ interrrupts are enabled (cannot see any other meaningful difference to start-up phase test since this test disables interrupts by itself so context switch should not happen while executing the test).
Is the interpretation correct? If yes, could you please list all SafeTI tests which should not be tried to run during runtime, pbists and so on are quite obvious but tests like this one isn't.