TMS570LS0714: DCAN global low-power PCR PSPWRDWNSET

Thanks for the clarification!

Chuck,
Thanks again for your feedback. We are now required to use the watchdog. This makes low-power mode tricky. The problem is we need relatively short DWD resets (< 1 second), but there are cases where the system should sleep for 10s of minutes. The best strategy I have come up with is to change RTI clock source from the default 8mHz clock to the LF LPO (effectively 40kHz). Then activate RTI compare 2, and disable the rest. This strategy covers about a minute of sleep time before the watchdog reset. This isn't ideal. But it's the best strategy I have come up with for the TMS570LS0714.

In an effort to increase the max sleep time I changed the RTI clock pre-divider from 2 to 8 (in RCLKSRC). I observed that if and only if I change this pre-divider, the system reboots almost immediately. I'm not sure if this is due to the RTI clock source not changing, or some other (default or halcogen generated) safety mechanism. For test sake, I lengthened the watchdog timeout to 2 seconds, and observed the system no longer resets. But, it comes out of sleep after 1-2 seconds due to the RTI compare 2 FIQ. This suggests the RTI clock source did not change.

Any insight you can provide will be much appreciated!

Thanks,
Stephen

Hi Stephen,

First I will address the elephant in the room. Having a WD service time of <1sec and a sleep time of 10minutes or more certainly seems to be conflicting requirements. None the less, it can be supported by simply waking every WD cycle to "pet the dog" then return to low power mode. This will dramatically impact your overall power consumption but is, realistically, the only way to maintain both requirements.

Essentially, you are going to have to weigh the power considerations of waking completely every WD period and running at some elevated speed to minimize the power up time vs. waking and using the LF LPO to execute code very slowly to service the WD. i.e., at very low frequencies, the device power consumption will be very small especially if you keep the modules you are not using in Low Power mode via the Peripheral PWR Down registers and only use the CPU running very slowly to service the WD.

As far as the unexpected behavior you are seeing, can you check the ratio of VCLK to RTICLK? According to the TRM this ratio has to be at least 3:1. Also, after making the update to the RTI clock divider, please allow some time for the clock to settle and the divider to take effect. Usually a few NOP instructions will provide adequate time.

Finally, from a safety consideration, are you using the on chip DWD? For certain, this is adequate for QM and maybe even SIL1 but for higher levels you should consider an external WD or at least the DWWD. For certain, if you do use either of the on chip watch dogs, please be certain that you have some independent monitoring of the device clocks for common cause concerns. i.e., if there is a fault in the device clock tree this fault could cascade into the DWD or DWWD and impact the effectiveness of those safety mechanisms to catch time based faults in the system.

Chuck. 

Thanks for your detailed response.  We are using the on-chip DWD.  I will double check the VCLK:RTICLK.  I may be turning off the VCLK. 

Stephen