This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS1227: Flexray network

Part Number: TMS570LS1227
Other Parts Discussed in Thread: TMS570LS3137, , HALCOGEN

The TMS570LS3137 Flexray  example use in TMS570LS1227 chip. can run?

  • Hello Zhang,

    no, you need some changes to device configuration: pinmux, PLL, device initialization, etc.
    1. Generate ccs project using HALCoGen
    2. Copy flexray related files to your new project
    3. Compile in CCS, if any errors, please let me know
  • Hello Wang ,
    I follow the step, but fauile.
    chk NDAT display 0,and Scope display Null frame.
    MBSC indecate Buf. chang.

    follw sprt718.pdf P37 affter config message, write WRHS1,2,3

    but output NULL frame.
    Thanks best regards
    Agassiz
  • Hello Chang,

    Can you show me the circuitry for flexray on your board? How many nodes are in your flexray network?
  • Th7633.flexray.pdf

    The cicuit boart attech.

    Totle 6 node,3 clodstart nodes, the orther are  sync nodes, in application network designed .

    now we try connect 2 coldstart and 1 sync node,

    gPayloadLengthStatic

    MHDC.SFDL[6:0]

    3C

    gColdStartAttempts

    SUCC1.CSA[4:0]

    31

    gListenNoise

    SUCC2.LTN[3:0]

    15

    gMacroPerCycle

    GTUC2.MPC[13:0]

    4

    gMaxWithoutClockCorrectionFatal

    SUCC3.WCF[3:0]

    15

    gMaxWithoutClockCorrectionPassive

    SUCC3.WCP[3:0]

    15

    gNetworkManagementVectorLength

    NEMC.NML[3:0]

    0

    gNumberOfMinislots

    GTUC8.NMS[12:0]

    0

    gNumberOfStaticSlots

    GTUC7.NSS[9:0]

    15

    OCS

    GTUC4.OCS[13.0]

    2250

    GTUC7.SSL[9:0]

    150

    gSyncNodeMax

    GTUC2.SNM[3:0]

    15

    gdActionPointOffset

    GTUC9.APO[5:0]

    2

    gdCASRxLowMax

    PRTC1.CASM[6:0]

    71

    gdDynamicSlotIdlePhase

    GTUC9.DSI[1:0]

    1

    gdMinislot

    GTUC8.MSL[5:0]

    4

    gdMinislotActionPoint

    GTUC9.MAPO[4:0]

    2

    NIT

    GTUC4.NIT[13:0]

    250

    gdSampleClockPeriod

    PRTC1.BRP[1:0

    0

    gdStaticSlot

    GTUC7.SSL[9:0]

    15

    gdTSSTransmitter

     PRTC1.TSST[3:0]

    4

    gdWakeupSymbolRxIdle

    PRTC2.RXI[5:0]

    59

    gdWakeupSymbolRxLow

    PRTC2.RXL[5:0]

    57

    gdWakeupSymbolRxWindow

    PRTC1.RXW[8:0]

    301

    gdWakeupSymbolTxIdle

    PRTC2.TXI[7:0]

    180

    gdWakeupSymbolTxLow

    PRTC2.TXL[5:0

    60

    pAllowHaltDueToClock

    SUCC1.HCSE

    1

    pAllowPassiveToActive

    SUCC1.PTA[4:0]

    15

    pChannels

    SUCC1.CCHA

    SUCC1.CCHB

    1

    1

    pExternOffsetCorrection

    GTUC11.EOC[2:0]

    0

    pExternRateCorrection

    GTUC11.ERC[2:0]

    0

    pKeySlotUsedForSync

    SUCC1.TXSY

     1

    pKeySlotusedForStartup

    SUCC1.TXST

    A=B=1, C=0

    pMacroInitialOffset[A]

    GTUC3.MIOA[6:0]

    5

    pMacroInitialOffset[B]

    GTUC3.MIOB[6:0]

    5

    pMicroInitialOffset[A]

    GTUC3.UIOA[7:0]

    12

    pMicroInitialOffset[B]

    GTUC3.UIOB[7:0]

    12

    pMicroPerCycle

    GTUC1.UT[19:0]

    40000

    The cicuit 

  • Hello Change,

    Your schematics look good. The configuration is not correct:

    gMacroPerCycle

    GTUC2.MPC[13:0]

    4

    The minimum macro per cycle is 10 per the flexray spec. You have 15 nodes and 15 slots for static segment, but you have only 4 macro for the whole communication cycle, how do you assign the macro to the slots?

    Your communication cycle has 40000 microticks (1 ms), this means your macrotick is 250us long. The Flexray says that the minimum macrotick is 1us and maximum macrotick is 6us.

    The microtick is 25ns (0.025us). And normally I configure macrotick to to 1us (40*microticks). Please correct your settings and try again. Thanks

  • hello Wang,
    sorry, it is wrong parameter.
    The config code in below.
    void configure_initialize_node_a(FRAY_ST *Fray_PST)
    {
    wrhs *Fr_LPduPtr=&Fr_LPdu;
    cfg *Fr_ConfigPtr=&Fr_Config;
    bc *Fr_LSduPtr=&Fr_LSdu1;

    Fray_PST->SUCC1_UN.SUCC1_UL = 0x0F1FFB00 | CMD_CONFIG;
    Fr_ConfigPtr->gtu1 = 0x000186A0;
    Fr_ConfigPtr->gtu2 = 0x000F09C4;
    Fr_ConfigPtr->gtu3 = 0x04041515;
    Fr_ConfigPtr->gtu4 = 0x094708C9;
    Fr_ConfigPtr->gtu5 = 0x38010303;
    Fr_ConfigPtr->gtu6 = 0x012D00Cd;
    /*Static segments */
    Fr_ConfigPtr->gtu7 = 0x000F0096; // NSS[25:16], gNumberOfStaticSlots = 0Fh; These bits configure the number of static slots in a cycle
    // SSL[9:0], gdStaticSlot = 150d = 96h (in macroticks); These bits configure the duration of a static slot.
    // Static segment length = 1150* 15 = 2250 macroticks
    /*Dynamic segments */
    Fr_ConfigPtr->gtu8 = 0x00000004;
    /* Action piont for Static, Dynamic and symbol window */
    Fr_ConfigPtr->gtu9 = 0x00010202;
    /*Clock Synchronization */
    Fr_ConfigPtr->gtu10 = 0x015100CD;
    Fr_ConfigPtr->gtu11 = 0x00000000; // pExternRateCorrection = 0, pExternOffsetCorrection = 0, no ext. clk. corr.

    Fr_ConfigPtr->succ2 = 0x00030F9A; // gListenNoise = Fh, pdListenTimeout = 224674d = 36DA2h

    Fr_ConfigPtr->succ3 = 0x000000FF; // gMaxWithoutClockCorrectionFatal = Fh , passive = Fh

    Fr_ConfigPtr->prtc1 = 0x000005F8; // pWakeupPattern = 2h, gdWakeupSymbolRxWindow = 76d,
    // BRP[15:14], Baud rate prescaler. BRP = 0: 10 MBit/s (Sample Clock Period = 12.5ns; 1 嚙踝 = 25ns; Samples per 嚙踝 = 2)
    // TSST(3-0), gdTSSTransmitter = Ah; These bits configure the duration of the transmission start sequence (TSS) in terms of bit times
    // (1 bit time = 4uT = 100ns @ 10Mbps).

    Fr_ConfigPtr->prtc2 = 0x00000000; // gdWakeupSymbolTxLow = 60d, gdWakeupSymbolTxIdle = 180d, gdWakeupSymbolRxLow = 18d, gdWakeupSymbolRxIdle = 18d

    Fr_ConfigPtr->mhdc = 0x0000003C;
    Fr_ConfigPtr->mrc = 0x00088080;

    // Output Buffer config initialization
    //Write Header Section Register 1 (WRHS1)
    Fr_LPduPtr->mbi = 1; // message buffer interrupt
    Fr_LPduPtr->txm = 0; // transmission mode - continuous mode
    Fr_LPduPtr->ppit = 0; // network management Enable
    Fr_LPduPtr->cfg = 0; // message buffer configuration bit (0=RX, 1 = TX)
    Fr_LPduPtr->chb = 1; // Ch B
    Fr_LPduPtr->cha = 1; // Ch A
    Fr_LPduPtr->cyc = 0; // Cycle Filtering Code (no cycle filtering)
    Fr_LPduPtr->fid = 0; // Frame ID

    //Write Header Section 2 (WRHS2)
    Fr_LPduPtr->pl = 0; // Payload Length

    //Write Header Section 3 (WRHS3)
    Fr_LPduPtr->dp = 0; // Pointer to start of data in message RAM

    Fr_LPduPtr->sfi = 0; // startup frame indicator
    Fr_LPduPtr->sync = 0; // sync frame indicator

    //input buffer configuration
    Fr_LSduPtr->ibrh = 0; // input buffer number
    Fr_LSduPtr->ibsyh = 1; // check for input buffer busy host
    Fr_LSduPtr->ibsys = 1; // check for input buffer busy shadow
    Fr_LSduPtr->ldsh = 0; // load data section
    Fr_LSduPtr->lhsh = 0; // load header section
    Fr_LSduPtr->obrs = 0; // output buffer number
    Fr_LSduPtr->rdss = 0; // read data section
    Fr_LSduPtr->rhss = 0; // read header section


    // Message buffers
    Fr_LSduPtr->lhsh = 1; // load header section

    // Buffer Key slot
    Fr_LSduPtr->stxrh= 1; // set transmission request
    Fr_LPduPtr->fid = 1; // frame ID
    Fr_LPduPtr->dp = 0x80; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 1; // TX frame
    Fr_LPduPtr->sync = 1; // sync frame indicator
    Fr_LPduPtr->sfi = 1; // startup frame indicator
    Fr_LPduPtr->pl = 0x3C;
    Fr_LPduPtr->crc = header_crc_calc(Fr_LPduPtr);

    Fr_LSduPtr->ibrh = 0; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // Buffer #1
    Fr_LSduPtr->stxrh= 0; // set transmission request
    Fr_LPduPtr->fid = 2; // frame ID
    Fr_LPduPtr->dp = 0x9E; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->sync = 0; // sync frame indicator
    Fr_LPduPtr->sfi = 0; // startup frame indicator
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 1; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // Buffer #2
    Fr_LPduPtr->fid = 3; // frame ID
    Fr_LPduPtr->dp = 0xBC; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->sync = 0; // sync frame indicator
    Fr_LPduPtr->sfi = 0; // startup frame indicator
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 2; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // buffer #3
    Fr_LSduPtr->stxrh= 1; // set transmission request
    Fr_LPduPtr->fid = 4; // frame ID
    Fr_LPduPtr->dp = 0xDA; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 1; // TX frame
    Fr_LPduPtr->sync = 1; // sync frame indicator
    Fr_LPduPtr->sfi = 0; // startup frame indicator
    // Fr_LPduPtr->chb = 0; // No transmission on Ch B
    Fr_LPduPtr->pl = 25;
    Fr_LPduPtr->crc = header_crc_calc(Fr_LPduPtr);

    Fr_LSduPtr->ibrh = 3; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);


    // Buffer #4
    Fr_LSduPtr->stxrh= 0; // set transmission request
    Fr_LPduPtr->fid = 5; // frame ID
    Fr_LPduPtr->dp = 0xF8;// Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->sync = 0; // sync frame indicator
    Fr_LPduPtr->sfi = 0; // startup frame indicator
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 4; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // buffer #5
    Fr_LPduPtr->fid = 6; // frame ID
    Fr_LPduPtr->dp = 0x116; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 5; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // buffer #6
    Fr_LPduPtr->fid = 7; // frame ID
    Fr_LPduPtr->dp = 0x134; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 6; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // buffer #7
    Fr_LPduPtr->fid = 8; // frame ID
    Fr_LPduPtr->dp = 0x152; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 7; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

    // buffer #8
    Fr_LPduPtr->fid = 9; // frame ID
    Fr_LPduPtr->dp = 0x170; // Pointer to start of data in message RAM
    Fr_LPduPtr->cfg = 0; // RX frame
    Fr_LPduPtr->crc = 0;

    Fr_LSduPtr->ibrh = 8; // input buffer number
    Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
    Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);
    Fr_ConfigPtr->mrc = 0x00208080; // LCB=0x17=23d: Last config buffer,# of msg buffer=0x17+1=24. >=80h, no message buffer configured; The maximum number of message buffers is 128
    // Wait for PBSY bit to clear - POC not busy.
    // 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
    while(((Fray_PST->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);

    // Initialize
    Fr_Init(Fray_PST, Fr_ConfigPtr);


    Fr_ControllerInit(Fray_PST);
    // Initialize Interrupts
    Fray_PST->EIR_UN.EIR_UL = 0xFFFFFFFF; // Clear Error Int.
    Fray_PST->SIR_UN.SIR_UL = 0xFFFFFFFF; // Clear Status Int.
    Fray_PST->SILS_UN.SILS_UL = 0x00000000; // all Status Int. to eray_int0
    Fray_PST->SIER_UN.SIER_UL = 0xFFFFFFFF; // Disable all Status Int.
    Fray_PST->SIES_UN.SIES_UL = 0x00000004; // Enable CYCSE Int.
    Fray_PST->ILE_UN.ILE_UL = 0x00000002; // enable eray_int1

    Fr_AllowColdStart(Fray_PST);
    }
    the node B has same Cycle parament. but diffrence buf arrange. key slot is fid=2;

    Please help me !

    Why does the Flexray Chennel Protocol controller sand null frame to bus?(Tms570LS1227)
  • macro per cycle 2500