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CCS/RM48L952: Clock Source Disable Register Inconsistency

bho
Prodigy 105 points
Part Number: RM48L952

Tool/software: Code Composer Studio

Hi,

The datasheet mentions

1.) 2.5.1.10 Clock Source Disable Register (CSDIS)

2.) 2.5.1.11 Clock Source Disable Set Register (CSDISSET)

3.) 2.5.1.11 Clock Source Disable Clear Register (CSDISCLR)

4.) 2.5.1.19 Clock Source Valid Status Register (CSVSTAT)

In code (and in the memory browser), I did a quick test to disable the Clock Source 1, the PLL1. In code, I disable PLL1 by setting bit 1 to 1 for CSDIS. Bit 1 is now set in both CSDISSET and CSDISCLR, and CSVSTAT shows bit 1 as 0, which indicates PLL1 is invalid. What I'm not expecting is CSDISCLR is also set to 1, which means the clock source is set to enabled state, but I just disabled it.

Next, I reset the system and do the same thing, except using the CSDISSET register bit 1. Bit 1 is set in both CSDIS and CSDISCLR register, and CSVSTAT bit 1 shows 0, which indicates PLL1 is valid. CSDISCLR is set to 1, which is not what I'm expecting.

So, from my testing, it feels like CSDIS and CSDISSET is mirrored from CSDISCLR, and CSVSTAT reflects the change as well.

CSDIS and CSDISCLR are mirrored from CSDISSET, and CSVSTAT reflects the change as well.

The above testing was done on the RM48L952PGE package.

  • 0
    TI__Guru 59540 points
    Hello Bho,

    In general, the SET and CLR registers will reflect the state of the register to which they are impacting. i.e., in this case, the read of these registers will reflect the content of the CSDIS register. It does seem that there is some inconsistencies in the description of the CSDISCLR register for the read values. A read of 0 should reflect that the clock source is enabled and a 1 indicate disabled as indicated in the description of the CSDIS register. I will enter a documentation bug on this topic so it can be updated in a future TRM release.

    CSVALID will indicate when the clock source is valid such that if CSDIS indicates disabled, CSVSTAT should reflect the same source as not valid.
  • 0 in reply to Chuck Davenport
    Prodigy 105 points
    Hi Chuck,

    Thanks for the reply. I have another issue with the CSVSTAT register. If I map PLL1 (Clock source 1) to GCLK, HCLK, VCLK, and VCLK2 Source Register (GHVSRC), bits 27-24 GHVWAKE to 1, and then I disable clock source 1 (PLL1) via either the CSDIS or CSDISSET register, the CSVSTAT register still shows that clock source 1 (PLL1) is still valid. Is this intentional?

    Thanks!
  • 0 in reply to bho
    Prodigy 105 points
    Looks like I found the answer to my question! Indeed, CSVSTAT shows PLL1 is valid, even though CSDIS shows PLL1 is disabled since clock domains are still mapped to PLL!

    10.5.2.2 PLL Disable
    The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source
    Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register
    (CSDISSET) of the System and Peripheral Control Registers. These bit allow the clock to disable but do
    not force the behavior until the clock is no longer used as the source for a clock domain (for example,
    GCLK, VCLK, VCLK2, RTICLK).
    The PLL receives a signal to disable after the clock is no longer used by any clock domain. Within the
    PLL, the clock is disabled and the appropriate CLKSRnV bit for the PLL in the Clock Source Valid Status
    Register (CSVSTAT), of the System and Peripheral Control Registers, becomes inactive. Then the PLL is
    placed into a low power state after the following length of time: