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TMS570LC4357: ADREFHI/ADC Faillure

Benjamin Couture
Prodigy 140 points
Part Number: TMS570LC4357

Hi,

We are develloping a new system with the TMS570LC4357. The system works fine in room temperature useage. But once we perfome thermal cycling testing (to 85C), the ADC fails. All the inputs gives the same proportional results, that is, for the same voltage, the results is the same. The ADREFHI draws 17mA and lowers the referance (2.8V instead of 3V). We have done the testing on multiples units and all seems to fails the ADC conversion. It is hard to troubleshoot them since they are casted in Nylon.

We are trying to find out what kind of failuer would cause the input of the ADREFHI to fail and draw higher current them the specs expect. All other voltage measured after the thermal cycling are normal and within specs. The only failling voltage is the ADREFHI.

If anyone has a similar issue or got a similare faillure of the ADREFHI, please let me know.

Some more details:

ADREFHI: 3V - REF5030AQDRQ1

ADREFLO: 0V

VCCAD: 3.3V - TPS65381QDAPRQ1

VSSAD: 0 V

One of my hypothesis is if VSSAD falls to 0V and that ADREFHI is still 3V, would the ADREFHI clamp in a short and damage the overvolatge clamps?

Ben

  • 0
    TI__Guru 59540 points
    Hello Ben,

    Can you clarify the voltage levels on Vssad and Vccad? What you have written would be backwards from what I would expect? i.e., VCCAD should be 3.3V and VSSAD should be the ground reference.
  • 0 in reply to Chuck Davenport
    Prodigy 140 points

    Hi Chuk,

    You are right, I inversed the two in my post. In reallity they are properly wired. Keep in mind, all those units works fine in normal température, it just fails after temperature cycling (~ 500 cycles)

  • 0 in reply to Benjamin Couture
    TI__Guru 59540 points
    Thanks for clarifying, Ben.

    Really, the only explanation I can offer is some sort of defect within the assembly or board that is causing a short or faulty connection somewhere. 85C is a relatively low temp for this device and I wouldn't expect there to be any issues. They are tested in production to 125C.

    When you stated that the adc results across all of the inputs are reacting in the same manner given the same inputs, can you identify if the results are reasonably accurate given the lowered ADCREFHI? i.e., is the ADC logic working properly?

    You mention the possibility of VCCAD=0V when ADREFHI = 3V, this condition would be concerning. There is definitely the possibility that this combination of ADREFHI>VCCAD could activate some parasitic leakage path in the device causing the excessive current and subsequent drop on the reference voltage due to the additional loading. If this occurs, the path could remain active until a scenario exists where it would be deactivated such as a power cycle and corrected relationship of VCCAD and ADREFHI that is within the limits identified in the datasheet (i.e., ADREFHI<=VCCAD).
  • 0 in reply to Chuck Davenport
    Prodigy 140 points

    Thanks for your input Chuck,

    Indeed, we use this chip in many of our line products. We usually don't have issues with them. That is why I'm trying to find out what kind of stress (electrical) would create a permanent damage on the chip (ADC section).

    I'm trying to find out before we start an other itération of the product validation. All those itération comes with a high cost.

    As for the ADC, the logic is good, the incrementations are proportional. But the 00h is high ~500mV. There really seems to be some kind of damaged in the ADC section.

    According to what you said, if VCCAD=0V when ADREFHI = 3V, it would create a temporary issue, but nothing that would permanently dammage the adc? (in a shortcircuit case the ADREFHI max would be ~20 mA). Even though I understand that you cannot troubleshoot from far, having an answer to that question would help in eliminating hypothisis.

    Thanks

  • 0 in reply to Benjamin Couture
    TI__Guru 59540 points
    Benjamin,

    I apologize for having stepped away from this thread for a bit and not getting back to you in an effective manner. To touch base, is this issue still ongoing?

    In response to your last post/statement, it would be expected that the leakage path would be present for the entire power on cycle of the device after the condition occurs. If with each subsequent power cycle the same even occurs, the same phenomenon is likely to be present. If you guarantee that VCCAD is never less than ADREFHI through a power cycle, does it still have the offset that you have described?