This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM44L520: GPIO input transition (rise and fall) time requirement question

Part Number: RM44L520

Hi Champion

A question from customer, from the datasheet, it require input signal Tin_slew within 1ns, then if the RC circuit in the IO input >1ns, what problem will cause?

Thank you!

  • Hello Eric,

    Thanks for this question. The specification is intended to identify the fastest rise time for an input that is allowed. i.e., the time from VIL to VIH should be no less than 1ns. This is a document bug since I believe your interpretation of it is the more literal meaning of the specification which does not align with our intent. I will enter a bug report to insure it gets repaired in an upcoming release of the datasheets for Hercules.Thanks again for pointing this out to us.

  • Hi Chuck

    Customer and I are confused as this data is different from the CMOS input transition timing, as below post and table in Figure 3.

    https://e2e.ti.com/support/interface/other-interface/f/146/t/473633

    If RM44 only has the MIN slew timing 1ns, then what is the MAX timing of signal from VIL to VIH. I suppose the input signal should not be so slowly. 

    Please also see this document: http://www.ti.com.cn/cn/lit/wp/slla364a/slla364a.pdf , cusotmer RC circuit in the GPIO input should not make the signal too slowly.

    ERIC

  • Hi Chuck

    Could you please help comment of additional questions?

    Thank you! 

  • Hello Eric,

    This is a device specific characteristic and will depend on device level implementation and process specific characteristics. The post you referred to and the able you posted is for another device that isn't even identified. I believe from the post that it is even an analog device so the characteristics and care abouts will be very different as the base building blocks, transistor types, process, and overall technology will be very different.

    The MCU input buffer does not "care" if the rise time is extended (slow slew rates) and it will not impact the physical circuit of the input buffer. However, it will impact the value that is seen by the MCU logic. i.e., we have a value for VIL, below this value we will see the input as a 0 and, likewise, we have a VIH value specified and above this voltage level we will always read the input as a 1. The specification of these values in the datasheet represents a commitment from TI that this will always be true. The logic that reads these inputs is digital logic so it will only be a 1 or 0. If the slew rate was very slow and a significant time is spent where VIL<VIN<VIH, the value that will be seen (1 or 0) from this input will be indeterminate. i.e., dependent on semiconductor process, supply voltage, and temperature, the read value may be either a 0 or a 1 and it would be the responsibility of the integrator to assure that the point of read is done in a repeatable/accurate manner. One method would be to understand the slew rate characteristics possible for the input and perform redundant reads of the IO outside of the rate of change of the input signal.

    If we consider the input characteristic of the question you linked to, the input frequency is 33MHz with a ~30nS ramp rate on the input voltage. This is well within a normal ramp for an input signal and I don't believe there would need to be any specific handling of the input needed. One could implement a redundant read of the input to assure that the value has "settled" and you are not reading at an input ramp intermediate value.