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RM48L952: IS the startup sequence in SPNA106D.PDF prescriptive?

Nick Chapple
Prodigy 100 points
Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hi. We have a product using the TI RM48L952 and have our own start-up code that was originally based on the HalCoGen code that met the SPNDA106D recommendations. For various operational reasons, we need to change the sequencing of some of the operations (such as initialising PINMUX or enabling FPU) so that operations are carried out later by the application rather than immediately on power-up by  the BSP.

My question is: Is the sequence ordering of the recommended steps in SPPNA106D mandatory, or is it just a guide? i.e. what do I risk by changing the sequence (assuming that irrespective of sequence I ensure I do not use anything until it is initialised)?

Many thanks

Nick

  • 0
    TI__Guru 59540 points
    Hello Nick,

    It is primarily just a guide. However, some things like CPU BIST and PBIST should be considered with some level of caution because they are destructive tests. Also, some proof tests (test of function) tests are also key to proving the mechanisms are working. This includes the ECC tests, CCMRx self test, and possibly WD tests. This would be mostly about proving the safe island functions are working. In generally, though, it comes to your system needs and your evaluation of the system level impact and requirements. As always, your application will determine your priorities and how you use the part.