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TMS570LC4357: how to force the cached data back into sram

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

I am using freeRTOS with MPU support and have created a task that has a non-cached shared memory so that the task can modify the buffer in shared screen buffer memory and the the DMA can access it to write to MibSPI.

I have created another task (in privilege mode) that updates the same screen buffer but MCU caches it and just lets the other task handle the DMA operation to copy to mibspi.

The problem is that the DMA transfer never sees the updates made by the other task.

I would like to know how to force the MCU to write back the cache data to sram so that the DMA can readout the expected data.

  • Hello Nino,

    I believe the solution is to configure that specific memory space as write through so that the actual SRAM is also updated instead of just the Cache. See MPU configuration in Halcogen.
  • Thanks Chuck.  I used that solution before.  I just wanted to try out something other than that.

    I've read up on commands available for cache (for invalidate and clean).   I've had added a _dcacheInvalidateRange_() before making changes to the shared memory location and using _dcacheCleanRange_() afterwards.   This combination resulted to the mibspi DMA being started on another task to read the screen buffer without issues.   Other combinations of cleanRange and invalidateRange did not work as expected.

    there might be some performance hit for this solution but works for me in the near term.