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TMS570LC4357: SCI TX DMA Problem

Ali Ghasemi
Prodigy 40 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi guys

I use the LAUCHPAD XL2 with TMS570LC4357. I'm new with DMA and after studying a lot of examples and TRM and datasheet, I wrote the program below using Halcogen.

I want to use DMA to transmit data by SCI1. As I know the program is correct. the sci transmits data out but the data is 0 except of the correct value. And of course the count is correct too.

please take a look at the code and tell me the problem.

SCI 1, Baud: 9600 No Parity

And please tell me why DMA needs the SCI1.TD register address to be plus 3 but sciSendByte uses just TD.

Thank you!6567.DMA.rar

  • 0
    TI__Guru**** 186196 points

    Hello Ali,

    1. DMA request for SCI3 TX is #31 rather than #29 used in your code

    2. TMS570LC43 is a big endian device, the TD[7:0] bit field is stored at the most upper storage address 

         SCITD[31:24] -- 0x38

         SCITD[23:16] -- 0x39

         SCITD[15:8] -- 0x40

         SCITD[7:0] -- 0x41

    3. Please add your code for receive to receive the txed data, then check if the rxed data is equal to the txed data.

  • 0 in reply to QJ Wang
    Prodigy 40 points

    Thanks bro.

    But I dont want to use SCI3. I want SCI1 TX.

    My HL_sys_main.cpp file was very untidy and it probably made you a mistake so I attach here the cleaned up code.  

    please take a look and tell me the problem. I just need a simple DMA SCI TX as an example. As I understand, DMA works but it reads data from somewhere wrong in memory because it sends correct number of bytes in SCI TX and I receive them in a terminal but the received bytes are all zero.

    0871.HL_sys_main.cpp

  • 0 in reply to Ali Ghasemi
    TI__Guru 59540 points

    Ali,

    Have you had a look at the application note Hercules SCI With DMA? It incldes example code as well but I believe it is not for the TMS570LC4357. Since the LC4357 has Cache, you need to insure the cache is configured for write through mode so that the data in RAM and Cache are guaranteed to match.

  • 0 in reply to Chuck Davenport
    Prodigy 40 points

    hey Chuck,

    Thanx for the hint. I disabled the cache in Halcogen: TMS570LC4357 > R5-MPU-PMU > Cortex-R5 > un check Enable Cache

    as the result, DMA worked! Now I want to act more professional. As I dont know anything about the Cache, would you plz send me some code about configuring it such as "write through mode" etc.

    that's so kind of you.

  • 0 in reply to Ali Ghasemi
    TI__Guru**** 186196 points
    Hello Ali,

    You can enable cache, and configure the memory regions as write through or write back (OIWT, or OIWB) through the HALCoGen.
  • 0 in reply to QJ Wang
    Prodigy 40 points

    Hi

    How can I know which part of memory should be configured

    Thanks

  • 0 in reply to Ali Ghasemi
    TI__Guru**** 186196 points

    Hello Ali,

    You can configure any memory region. The MPU on LC43x supports up to 16 regions. If the SRAM (staring from 0x08000000) is used as the src/dst address for the DAM transfer, you can configure this memory region as OIWT (write through).