Hello,
The workaround suggested in technical note SPNA233A recommends to perform up to 5 PLL lock retries at a specific frequency to impove lock time, however could you please calrify the following points:
- Would performing the lock procedure at the final user expected PLL frequencies only impact the actual lock sequence time or would it jeopardize the lock success rate ?
- Would performing each of the lock procedure attempts after a complete system warm reset and not in a row after a single power on reset would jeopardize the lock success rate ?
- Can you please clarify what is the recommended procedure in case the PLL is still not locked successfully after five attempts, would you recomment to perform additional retries or to perform a power reset before trying to lock again ?
- Are there specific environmental conditions that would impact the occurence rate ?
- Would you have actual figures to quantify the "rare" occasion rate ?
Thanks,