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TMS570LC4357: PLL startup Errata SSWF021#45

Part Number: TMS570LC4357

Hello,

The workaround suggested in technical note  SPNA233A recommends to perform up to 5 PLL lock retries at a specific frequency to impove lock time, however could you please calrify  the following points: 
 

  1. Would  performing the lock procedure at the final user expected PLL frequencies  only impact the actual lock sequence time or would it jeopardize the lock success rate ?
  2. Would  performing each of the lock procedure attempts after a complete system warm reset and not in a row after a single power on  reset would jeopardize the lock success rate ?
  3. Can you please clarify what is the recommended procedure in case the PLL is still not locked successfully after five attempts, would you recomment to  perform additional retries or to perform a power reset before trying to lock again ? 
  4. Are there specific environmental conditions that would impact the occurence rate ?
  5.  Would you have actual figures to quantify the "rare" occasion rate ? 

Thanks,

  • Hello Frank,

    Thank you for your very appropriate and well stated questions on this subject matter. In order to better support you, I am notifying the author of the application note and the advisory in the errata document since they will be much better suited to provide you with answers.

    I will continue to monitor this thread, so if there is anything additional that I can do to help please let me know.
  • Franck WARTEL said:
    Would  performing the lock procedure at the final user expected PLL frequencies  only impact the actual lock sequence time or would it jeopardize the lock success rate ?

    Yes, the settings chosen provide a high frequency of feedback clocks that optimizes the startup of the VCO. Other settings are slightly less successful.

    Franck WARTEL said:
    Would  performing each of the lock procedure attempts after a complete system warm reset and not in a row after a single power on  reset would jeopardize the lock success rate ?

    Once the VCO has successfully started after a power-on, it is no longer necessary to run the work-around code. Notice that the number of retries passed to the work-around routine is really a maximum for time-out purposes. Once the VCO starts and the PLL locks correctly, the routine exits. Using less than 5 attempts, reduces the effectiveness of the work-around. Increasing the number of retries increases the effectiveness, but at a much diminished rate.

    Franck WARTEL said:
    Can you please clarify what is the recommended procedure in case the PLL is still not locked successfully after five attempts, would you recomment to  perform additional retries or to perform a power reset before trying to lock again ? 

    This really depends on the needs of the application. Some customers set retries to zero, causing the maximum number of retries to be infinite. Others cause a system reset, which often equates to the same effect, infinite retries. Others, continue to operate at the crystal frequency but with limited functionality and have the MCU provide some fail mode indication. It would be ideal to remove power and reapply it. Simply asserting the nPORRST without removing power is no more effective than just a software reset.

    Franck WARTEL said:
    Are there specific environmental conditions that would impact the occurence rate ?

    Each device that has the possibility of this failure mode will show it in a small temperature/voltage window. Unfortunately the temperature and voltage where the failure occurs is unique to each device. In general, more devices fail at cold temperatures, but some devices fail at mid and high temperatures.

    Franck WARTEL said:
    Would you have actual figures to quantify the "rare" occasion rate ?

    Our testing using 5,000 power-on cycles equally distributed over the ambient temperature range of -40C to 125C using the work-around with 5 retries predict a failure rate of approximately 30 DPPM (defective parts per million).

  • Hello Bob,

    Thanks for those clear answers.

    I only have one question left regarding independence of the failure mode.
    You stated that each device has the possibility of this failure mode occurrence at different temperatures or voltage, is it true even for dies coming from the same wafer ?
    In other word in a redundant architecture would the end user have to pay a specific attention to the actual wafer source or die location to be able to sustain that there is no common failure mode, or is the failure mode independent whatever the devices come from ?

    Thanks for your support,

    Regards,

    Franck
  • Hello Franck,
    One minor correction, not all devices have the possibility of this failure mode, in fact very few do. My statement was "Each device that has the possibility of this failure mode will show it in a small temperature/voltage window."

    We have looked extensively for a correlation to lot, wafer, die location on the wafer and process. None of these parameters correlate to the possibility of this fail mode.
  • Thanks for this last answer.

    I now have sufficient material to complete this errata analysis.

    Best Regards,

    Franck