Hello
I'm using 12 SRAM on three different banks of my processor. I'm to calculate current requirements that either I need a buffer or not. One Cs enables 04 SRAM at one time.
As the Adress bus, and control signals. For current calculations, of writing or reading on one bank, should I add the input capacitance (address pins) of all other 08 SRAM (whose cs is high) or only consider their leakage current? I believe leakage current is very low and input capacitance needed to account while reading or writing on high speed. If the pins are going into high impedance when CS is not active what it means in terms of current requirement.
Regards;
