Other Parts Discussed in Thread: HALCOGEN
Hello,
I am struggling to create a test case to generate DCC errors or the RM48L952. It is our OE designed PCB and we use a 20MHz clock. We would like, but do not have to, detect drift in the OSCIN relative to another clock such that we can safely act upon a % excurision from nominal in a safe manner. The approach we are taking is to replace the OSCIN with a signal generator and change the input frequency up and down in an effort to trip the system with the appropriate ESM error logged. We never get DCC to trip, we always end up down at ~2.2MHz and an LPO trip. The ESM logic, nError activity and everything else we have in place makes sense and appears to work but we have not been able to create a test that will deliver DCC trips. I attach an example of our HALcogen configuration, where we look to check PLL against OSCIN. Can anyone point me to the flaws in our approach?
Thanks
Jamie