RM48L952: SDRAM error

Michael Jensen44

Prodigy 90 points

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

I have used HALCOGEN to initialize the SDRAM on the RM48 development kit and i am running a RAM test.

If i write 0x8A00 to any adress of the SDRAM i read back 0x8A008A00.

i am hoping it is a config problem.

the halcogen default EMIF clock is 110MHz and the SDRAM is 143 MHz is this a problem

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 186226 points

Michael,

Can you please lower the EMIF clock to 80MHz or 60MHz, then do a test?

0 Michael Jensen44 over 5 years ago in reply to QJ Wang

Prodigy 90 points

Hey QJ

i can change my VCLK3 to 73.33 this helped with my mirroring problem in the high and low part of a 32 bid address space, however i now find that my base address (0x80000000) is mirrored in the address 0x80800000, 0x81000000, 0x81800000, 0x82000000, 0x82800000, 0x83000000 and 0x83800000

1. how come i need to use a 73.33 MHz clk for a 134 MHz SDRAM

2. is it correct to assume that when using the IS42S16400J SDRAM 1 Mbit x 16 bits x 4 banks i have access to all addresses from 0x80000000 to 0x83FFFFFF

0 QJ Wang over 5 years ago in reply to Michael Jensen44

TI__Guru**** 186226 points

Michael,

Yes, you can access the whole address range of IS42S16400 SDRAM.

0 Sunil Oak over 5 years ago in reply to Michael Jensen44

TI__Mastermind 49120 points

Hi Michael,

The max SDRAM clock specified in the datasheet is 110MHz.

Also, the total addressable memory for an external SDRAM is 128MB. You are connecting an 8MB memory, hence the mirroring throughout this 128MB space every 8MB (0x80000000, 0x80800000, 0x81000000, ...)

Regards,
Sunil

0 Michael Jensen44 over 5 years ago in reply to Sunil Oak

Prodigy 90 points

I see my mistake regarding the amount of address space thank you for the clarification.

What i do not understand is that i get a mirror pattern between the upper and lover 16 bits of any address if i run the SDRAM clk at 110MHz

0 Sunil Oak over 5 years ago in reply to Michael Jensen44

TI__Mastermind 49120 points

It could be due to an issue with configuring the timings for the SDRAM at 110MHz. I will check in more detail tomorrow and let you know.

Regards,
Sunil

0 QJ Wang over 5 years ago in reply to Sunil Oak

TI__Guru**** 186226 points

Hello,

The maximum EMIF clock is 55MHz.

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RM48L952: SDRAM error