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Original question:

TMS570LC4357: MDIOPhyRegRead

TMS570LS1227: MDIOPhyRegRead

Michael Warmers
Prodigy 130 points
Part Number: TMS570LS1227
Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm using the Hercules Safety MCU Development Kit - TMS570 MCU.
It embeds the MCU TMS570LS1227.

When calling MDIOPhyRegRead() with
-baseAddr = 0xFCF78900 ( = mdioBaseAddr )
-regnum = 2            ( = PHY_ID1      )

The function gets stuck in the 2nd while loop, where it polls for completion:

while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO)

Any idea, what could be wrong?

BTW: EMACInit() and MDIOInit() are called.

Best regards
 Michael

 

  • 0
    TI__Guru**** 186276 points
    Hi Michael,

    Is MDIO_USERACCESS0 0x80? or MDIO_USERACCESS0=0xFCF78980 in your code? Please check the pinmux as well. The MDIO and MCLK are muxed with NHET.
  • 0 in reply to QJ Wang
    Prodigy 130 points
    Hello Wang,

    thanks for fast response. Meanwhile I had minor success after some trials with a changed HAL. But now I'm struggling two lines later at
    if(((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK) == MDIO_USERACCESS0_ACK).
    I do not get the acknowledge.

    Regarding your question: MDIO.USERACCESS0 = 0x0041FFFF
    I guess you mean I should check the Halcogen PINMUX tab. Unfortunately I'm missing the experience for such a check. Since I am using a development kit ... could it be that there is an ready to use Halcogen configuration available somewhere?

    What I see in my Halcogen is Ball G3 is connected with MDIO.
    And ball V5 with MDCLK. I assume this is the MDIO clock!?
    How to verify that this is the correct setting?

    Best regards
    Michael
  • 0 in reply to Michael Warmers
    TI__Guru**** 186276 points
    The pinmux settings are correct if G3 and V5 are checked for MDIO and MDCLK. You can double check the registers of pinmmr7 and pinmmr8 in CCS register window (CCS->View->Registers). The bit field [11:8] should be b0100 (bit 10 is set).

    BTW, the MDIO clock (MDCLK) should be <2.5MHz.
  • 0 in reply to QJ Wang
    Prodigy 130 points
    Hello Wang,

    thanks for your support. Meanwhile I was able to resolve it:

    The main trouble for the "Hercules Safety MCU Development Kit - TMS570 MCU" is the missing documentation. Unfortunately I was expecting that the EMAC/PHY was usable with the default settings of the DIP switches. So far I found no hint that the boards DIP switch default setting is "ETHERNET off". Moving the switch to "on" is the resolution!

    Regards
    Michael
  • 0 in reply to QJ Wang
    Prodigy 130 points
    Hello Wang,

    it is working now. But I just want to double check for the following:
    >>BTW, the MDIO clock (MDCLK) should be <2.5MHz.
    Where can I find the MDIO/MDCLK clock setting/configuration? I expected to find the setting in Halcogen, but I was not successful.

    Regards
    Michael
  • 0 in reply to Michael Warmers
    TI__Guru**** 186276 points
    Hi Michael,

    It is on page 1837 of the TRM: spnu515b.pdf

    32.2.1 Clock Control

    All internal EMAC logic is clocked synchronously on the VCLKA4 domain. Please refer to the Architecture
    chapter for more details.

    The MDIO clock is based on a divide-down of the VCLK3 peripheral bus clock and is specified to run up to
    2.5 MHz (although typical operation would be 1.0 MHz). Because the VCLK3 peripheral clock frequency is
    configurable, the application software or driver must control the divide-down value.