TMS570LC4357: Requesting assistance for ETM trace init on TMS570LC

Hello Nino,

The ETMDATA[7:0] signals are not multiplexed with other signals. You don't need to worry about the pinmux (input or output) for those 6 signals. What is the ETM issue you ran into? Is there a series termination resistor on ETMTRACECLK* signals to minimize the reflection?

Hi QJ,

Thank you for your quick reply.
Here is the error description from our mail correspondence with TI:

The unexplainable behaviour is as follows:
- Activate VCLK->Enable PD2 clock domain->Init TPIU to 4-bit trace (+ TPIU_CLKSEL register), TF and ETM as usual
- We now get a traceclock (4 MHz default after reset without PLL init) and trace bits 1-3 are active. Bit 4 however stays at 0 V. We double checked the connection from the BGA to the trace header on pass through and everything was connected correctly
- At the same time, while the target is halted we would expect the TPIU to send out half-syncs which are usually something like 0xFFF7FFF7. However as mentioned before Bit 4 stays flat and Bits 1-3 are not staying at 1 as expected but dip to 0 in between.
We would expect bits 0-2 to stay "high" for the half-syncs, however this is not the case here.

We can't really explain ourselves why Bit 4 is not active at all even though the TPIU is initialized correctly. Pins used as referenced in the target devices manual:
TLCK R10
TD0 R12
TD1 R13
TD2 J15
TD3 H15
So either Bit 4 needs to be initialized extra or the Pin out in the manual is not correct.
Also this is the first time we see half-syncs being output as pictured.

Could you provide us with the init steps that TI was using for verifying trace functionality on the TMS570LC?
We assume there is still some target specific init that we are not executing properly.
Do you have additional internal trace documentation that might help us out here? In the public documentation I could not find any hints for extra trace registers other than the ones we already configure.

Best regards,
Nino

HI Nino,

For more details about ETM, see the ARM CoreSight ETM-R5 TRM specification

infocenter.arm.com/.../DDI0480B_coresight_soc_r1p0_trm.pdf

TI doesn't have appnote and example code for ETM.

Hi QJ,

We are aware of the ETM and coresight specifications... We already support several hundred Arm devices with our Trace probe which works out-of-the-box in each case so we have some knowledge when setting up trace.

In this case we are following exactly all Arm specified init steps. Unfortunately the TMS570LC does not behave as specified by Arm.

BTW the manual you linked lists only a couple of Coresight components, e.g. ETM is not even described in there as ETM has its own Arm manual.

FYI the TMS570LC is using ETMv3.4 if you are curious.

Anyways our questions boil down to the following two:

- Does ETM pin trace work on the TMS570LC with other trace probes that are on the market?

- If yes, could you provide us with the same information our competitors got that are not documented in public manuals?

Best regards,

Nino

Hi Nino,

One of my coworker did ETM test using XDS560V2 Pro Trace for trace and TMS570LC4357 HDK with 60-pin MIPI connector.

I hope this one is helpful for you:
www.ti.com/.../spru655i.pdf

Hello QJ,

OK good to hear that there is a setup with which it is working with.

Unfortunately the provided document does not tell anything about the initialization for the TMS570LC but only handles general Trace and signal knowledge.

Could you provide us with the same information that the XDS560V2 Pro Trace guys were provided with?

Could you provide us with the exact register settings of all trace related coresight modules on the TMS570LC that the XDS probe sets?

Alternatively, could you provide us temporarily with the XDS probe for reproduction so we can check the register settings our selves?

Best regards,

Nino

Hi Nino,

I am sorry I don't XDS probe, and I don't know where XDS team got the information.

Hi QJ,

OK, could you provide us with a TI contact that might know?

We would really appreciate your assistance here as a TI tool partner.

Best regards,

Nino

Ok, I will ask the expert in emulation team to chime in.

Any news?

Are there any news on this topic?

Hello Nino,

I am sorry that I don't have extra information regarding ETM configuration and initialization.

Hello,

OK to summarize, there is no one at TI who knows how the device specific initialization (which is not in the public documentation) to enable tracing works?
Under that prerequisites we have to pull any mention of trace support from our website for the TMS570 and RM57 series.

Best regards,
Nino

Hello Mr Wang,

I would like to know if we can expect more informations from the support team. What I would expect is a clear statement, on why you don’t want to provide this information, because it is hard to believe that no one in your company  knows how to configure the trace.

Thanks for your reply, and best regards,

Guillaume

Hello Guillaume，

The TMS570LC4357 contains a ETM-R5 module with a 32-bit internal data port. The ETM-R5 module is connected to a Trace Port Interface Unit (TPIU) with a 32-bit data bus. The ETM-R5 follows the ETM v3 specification. For more details, see the ARM CoreSight ETM-R5 TRM specification:

infocenter.arm.com/.../DDI0469B_etmr5_r0p0_trm.pdf

Spectrum digital developed a trace analyzer: XDS560v2 PRO TRACE Receiver & Debug Probe. And this tool works on TMS570LC4357 HDK to trace the ETM data under TI code composer studio.

ETMDATA[7:0] are not multiplexed with other functionality (no pinmux is required for those pins). If the signal trace and connection is ok, this pin should work without any issue.

Hello QJ,

As metioned in the first message of this thread, the pins related to tracing feature are not fully documented in the spnu563a (missing ETM data[0..4]). Is threre any reason for that? Because Mr. Peck (also in the first message) seemed to think to an incorrect mux configuration. As you are saying the opposite, it is hard to know where is the truth. That's why I'm asking if it would be possible to correct the latter document (spnu563a) by documenting those pins?

Best Regards, 

Guillaume

Hi Guillaume,

The ETMDATA[7:0] are not multiplexed with other functionality (Table 6-1, and Table -19). They are only used for ETM.

Hi QJ,

Thanks for your quick reply. Could you send a screenshot where you find the ETMDATA[0...7] in table 6-1 please? Because I'm not able to find them. I noticed that the balls T4 and U7 are not multiplexed either, but are still documented in the table 6-1 (page 307 of spnu563a), thus, there is no reason for others balls (such as ETMDATA[0...7]) for not being documented as well I guess.

Thanks and Best Regards,

Guillaume

Hello Guillaume,

Since ETMDATA[7:0] are not muxed, those signals are not listed in Table 6-1. The table 4-19 shows that those terminals (R12, R13,...E14) are only for ETM data (ETMDATA[7:0]).

Hello Mr. Wang,

Ok, it is not a pin mux problem. Then is your reply from the 16 january the official TI’s answer for this thread? Should we assume, as customers, that no one in your company (the same as the one who designed this MCU) will be able to provide some help about this topic?

Best Regards,

Guillaume

Hi Guillaume,

I can try the ETM using XDS560V2 Pro trace to see if there is the problem you mentioned.

Hi QJ,

Thank you for your reply. Would it be possible to dump the memory related to TPIU once initialized, and share the probe's log to see what it does for initalizing it?

Thanks and best regards,

Guillaume

Hi QJ, Thank you for your feedback. Good to see it working! Would it be possible to try it with 4 data lines as well? And would it be possible to get the logs output of the debug session from the XDS560V2 as well? And, if possible, a dump of the peripheral’s memory which might impact the tracing feature (TPIU, clocks, IO,...)? Thanks in advance for your help, Guillaume

The right-top corner is the memory content of ETM registers:

1. ETMCR =0x00023C1C-->trace instruction+data, port size=b0101
2. ETMCCR=0x8D254024
3. ...