TMS570LS3137: Need more details on VimParity Handler

sreenivasan m

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi Team,

This is regarding the Halcogen code generated for TMS570LS3137 controller. From sys_vim.c file, vimParityErrorHandler has below piece of code:

vimParityErrorHandler(void)

{

.....
Correct the corrupted location, clear parity error flag.

Now, we have a comment to disable and enable the highest priority pending channel. But, we are checking onlly for vector 0 not for other vectors.
Does it not require to consider for all vetors and disable it by updating corresponding IRQINDEX register?

}

Please let me know more details on this.

over 5 years ago

0 Sunil Oak over 5 years ago

TI__Mastermind 49120 points

Hi Sreenivasan,

There is checking for other interrupt channels as well. Channel 0 requires special consideration as it is driven by the ESM high-level interrupt.

Regards,
Sunil

0 sreenivasan m over 5 years ago in reply to Sunil Oak

Genius 3705 points

Hi Sunil,

Sure, but there are other interrupt pins which needs to be clear, but we are clearing only for pin 0. Believe, clearing of pins other than 0 is also required. Please confirm.

Regards,
M.Sreenivasan.

0 Sunil Oak over 5 years ago in reply to sreenivasan m

TI__Mastermind 49120 points

Hi Sreenivasan,

The vimParityErrorHandler() does include checks for other interrupt request numbers as well. Below is the full function:

void vimParityErrorHandler(void)
{
    uint32 vec;
    
    /* Identify the corrupted address */
    uint32 error_addr = VIM_ADDERR;

    /* Identify the channel number */
    uint32 error_channel = ((error_addr & 0x1FFU) >> 2U);

	if(error_channel >= VIM_CHANNELS)
	{
        /* Index is out of bonds */
        /* This condition should never be true since the HW only implements VIM_CHANNELS (96) channels */
        /* However, it was added due to defensive programming */
/* USER CODE BEGIN (2) */
/* USER CODE END */
	}
	else
	{
		/* Correct the corrupted location */
		vimRAM->ISR[error_channel] = s_vim_init[error_channel];

		/* Clear Parity Error Flag */
		VIM_PARFLG = 1U;

		/* Disable and enable the highest priority pending channel */
		if (vimREG->FIQINDEX != 0U)
		{
			vec = vimREG->FIQINDEX - 1U;
		}
		else 
		{
		   /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Read 32 bit volatile register" */
			vec = vimREG->IRQINDEX - 1U;
		}
		if(vec == 0U)
		{
			vimREG->INTREQ0 = 1U;
			vec = esmREG->IOFFHR - 1U;
			
			if (vec < 32U)
			{
				esmREG->SR1[0U] = (uint32)1U << vec;
				esmGroup1Notification(vec);
			}
			else if (vec < 64U)
			{
				esmREG->SR1[1U] = (uint32)1U << (vec-32U);
				esmGroup2Notification(vec-32U);
			}
			else if (vec < 96U)
			{
				esmREG->SR4[0U] = (uint32)1U << (vec-64U);
				esmGroup1Notification(vec-32U);
			}
			else
			{
				esmREG->SR4[1U] = (uint32)1U << (vec-96U);
				esmGroup2Notification(vec-64U);
			}
		}
		else if (vec < 32U)
		{
			vimREG->REQMASKCLR0 = (uint32)1U << vec;
			vimREG->REQMASKSET0 = (uint32)1U << vec;
		}
		else if (vec < 64U)
		{
			vimREG->REQMASKCLR1 = (uint32)1U << (vec-32U);
			vimREG->REQMASKSET1 = (uint32)1U << (vec-32U);
		}
		else
		{
			vimREG->REQMASKCLR2 = (uint32)1U << (vec-64U);
			vimREG->REQMASKSET2 = (uint32)1U << (vec-64U);
		}
	}
}

The highlighted code checks for interrupt sources other than channel 0, disables that interrupt channel and re-enables it.

Regards, Sunil

0 sreenivasan m over 5 years ago in reply to Sunil Oak

Genius 3705 points

Hi Sunil,

Sorry, I could not see highlighted part, but, i believe you are pointing to all else if (vec < 32U) and so on cases.
But, in all these elseif's, we are setting(writing 1) CLR and SET registers which actually enables the interrupt (as per SPNU499c.pdf).
Where exactly we re disabling interrupts for other than channel 0. Why not we are clearing the interrupts using INTREQx (x can be 0, 1, 2)register?

Regards,
M.Sreenivasan.

0 Sunil Oak over 5 years ago in reply to sreenivasan m

TI__Mastermind 49120 points

Hi Sreenivasan,

Writing '1' to a bit in the *CLR register disables the corresponding interrupt channel.

Writing '1' to a bit in the *SET register enables the corresponding interrupt channel.

It is done specifically so that the application can avoid a read-modify-write operation each time it needs to enable or disable any single interrupt channel.

There are also similar *SET and *CLR registers in several modules that control different functionality.

Regards,

Sunil

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TMS570LS3137: Need more details on VimParity Handler