TMS570LC4357: MibSPI sequencer reset

If the transfer group is configured as one-shot, the transfer is performed only once. The transfer group needs be reconfigured for next transfer (mibspiRAM-> tx.control). The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data.

What is the trigger type and trigger source used in your code?

The transfer group has oneshot enabled, trigger event is 'always' and trigger source is disabled. This is a slave SPI configuration using one transfer group with 4 DMAs (2 for rx and 2 for tx) each DMA moves half of the data into and out of the mibspiRAM. The mibspi DMA has oneshot disabled, which may be a factor here. I want the slave device to be available as much as possible so that if a master initiates multiple data transfers, it will get a valid response for each transfer, however I need the slave to be able to modify the data periodically.

Additional info:

My transmit data is double buffered, when I swap the buffers I need to be sure that the tx shift register is updated with the first byte of the new buffer.

I just run MibSPI+DMA to transmit data from MibSPI1 to MibSP3, I did not produce the issue. I use one DMA channel for one group.

Hi QJ,

The SPI and DMA appear to be working, but my scenario is a little different. I am periodically changing the DMA source address (swapping buffers) to point to new data. It appears as though the first byte of the next transmission is from the previous DMA source address. I think this is because the SPI sequencer puts the first byte into the tx shift register immediately after the SPI transfer ends and doesn't update it when I modify the DMA source address. I want to ensure that the sequencer updates the tx shift register when I swap the DMA source address so that the next SPI transfer has the correct first byte.

Hello Jeremy,

Sorry for the delay, I will do a test, then come back to you later today.

Hello Jeremy,

If oneshot is set in DMACTRL register, the transfer is performed only once.

You can use 2 DMA channels for data transfers, each has its own configuration (source addr, destination addr, etc). MibSPI supports up to 8 DMA channels for TX and RX. ALl the DMA channels are imdividually programmable and can be hooked up to any buffer in the multibuffer RAM.

Can you share your code or part of your code? I am doing a test, but haven't make it work.

Hi QJ,

I'm unable to share my code publicly, but I could share it privately as long as my company's agreements with TI are still valid.

I can try to provide some additional detail. I have SPI1 set up as a slave device using one TG with 8 buffers, the data word format is setup to transfer 8-bits of data for each TG buffer. I'm using 4 DMAs to transfer 4 bytes of data into/out of the buffers (2 rx and 2 tx). The DMAs are triggered on buffers 3 and 7. The total data packet size is 1024 bytes, but these data packets are double buffered so the application reads/writes to one set of data packet buffers and the SPI/DMA uses the other set. I have 2 periodic tasks set up (2.5ms and 5ms). The 2.5ms task checks if a SPI transfer has completed (DMA BTC flag is set for all 4 DMAs and a SPI transfer is not in progress (i.e. the SPI TG Triggered flag is not set)). If a transfer has completed, the DMAs are reconfigured to point to the other buffers, i.e. the double buffers are swapped, and the DMAs are triggered to populate the TG buffer with the data from the new buffer the DMA is pointing to. This is where I need the shift register to update as the previous DMA trigger seems to have loaded the previous buffer's first byte into the shift register at the end of the previous SPI transfer.

In the 5ms task the Application is updating the data in the transmit buffer that it is currently pointing to.

Hello Jeremy,

Thanks for providing the details of your DMA settings. I try to do the same test after I get back from my travel. If the DMA transfer is configured as on-shot, the DMA transfer is only performed once. The MibSPI transfer is only triggered by the chip-select signal (level-sensitive trigger).