CCS/TMS570LC4357: EMIF 16 bit memory interface

As per the reference manual figure 21-8 we were expecting the data to be mapped as follow:

but the last bit is not at all coming.

Thanks Miro for looking into this issue.

Yes, actually this would be the expected behaviour.

but as per the case: 

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/312729/1757527?tisearch=e2e-sitesearch&keymatch=EMIF%20hercules%20questions%20anila#1757527

if the memory is x16 then you only get A[1] on BA[1] and A[0] becomes an MSB.

Can you please explain this behaviour?

Secondly, When writing to a particular address, along with the required address 2 more address locations are also accessed. Please see the below FPGA debug capture for details.

Here SW is accessing address 0x000F(Actual address written is 0x1E, Since last bit is not transmitted, FPGA is receiving it as 0x000F). Along with this 2 more addresses are accessed. In the figure you can see when CS becomes low, 3 address locations are accessed, 0x00D,0x00E,0x00F. Only the last one is the correct one. 

Can you please provide us the details about it, this really will be helpful.

Regards,

Shivam Kakad

Hello,

If the memory is 16 bit, address 0 of the memory A[0] should be connected to EMIF BA[1], and address A[1] of the memory is connected to EMIF_A[0].

Best regards,
Miro

Hi Miro,

Can you please give us a complete address mapping for 0X600000A5 which will be clearer for us. Quick response is highly appreciated.

Since, per below link(https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/312729/1757527?tisearch=e2e-sitesearch&keymatch=EMIF%20hercules%20questions%20anila#1757527), "But if the memory is x16 then you only get A[1] on BA[1] and A[0] becomes an MSB".

Can you confirm, is the information in above link is correct?

Part Number: TMS570LC4357

Hi Team,

1.As TRM (spnu563.pdf), below are the required connections between EMIF and asynchronous device in 16 bit mode.

.

But as per the case, Since, per below link(https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/312729/1757527?tisearch=e2e-sitesearch&keymatch=EMIF%20hercules%20questions%20anila#1757527), "But if the memory is x16 then you only get A[1] on BA[1] and A[0] becomes an MSB".

The above statement and diagram in TRM differs connection wise. Can you please help in clarifying this? Is the statement mentioned in above case is correct?
Also, could be great if you can mention values on address lines for 0x6000000A5?

We could see in this case, we getting below values on EMIF address lines(when connections were made as per the above diagram):

• BA1 – 0, A0 – 1, A1- 0,A2 – 0, A3 – 1, A4- 0,A5 - 1

Also, we could see below behaviour during write operation.

2.After chip select low, before WE low, does the data available in address lines are valid?
Our observation is that the values on the address lines are invalid (Not the one which controller is expecting), but when WE pin is low, during this time, valid address is present.
Is this is an expected behaviour?

Can someone comment on this case and answer to above questions please?

Thanks Miro. How to interpret this value as A5 from Flash end. Can you help in this?

And can you please explain about us on the second behaviour that is asked above, regarding the values on the address lines are invalid (Not the one which controller is expecting), but when WE pin is low, during this time, valid address is present.?

Thanks Miro for providing the explanation with diagram. So, If I understood correctly, we should always access 16 bit alignment address and not the odd address.

For the second point, is the values in address lines (intermittent values) prior to WE pin low behavior is expected?

Thanks Miro. We are able to get the valid address during strobe period and not in setup period. Please let me know if we need to capture further details to debug this further?

Hello,

How are you triggering the oscilloscope?
Are you sere that address is not valid in a moment before WE goes low?

Best regards,
Miro

Hi Miro,

Yes, we captured the snapshot in FPGA when it was connected with FPGA.

Any updates on this behavior and way forward Miro?

Hi Miro,

Please confirm:
From controller side, if we send 0x1E (last byte of address), controller right shifts its value by 1 (0xF) and send out when connected with 16 bit async device.
So, inside Async device, we need to left shift by 1 in order to access the same address in Async.

Yes Miro. Can we have generic comment as below:

From controller side, if we send 0x1E (last byte of address), controller right shifts its value by 1 (0xF) and send out when connected with 16 bit async device.
So, inside Async device, we need to left shift by 1 in order to access the same address in Async.

And also, the address value issue on the address bus after chip select low and prior to write enable low?

Can you please confirm?