TMS570LC4357: Changing cache size

Zakaria Nakrachi

Part Number: TMS570LC4357

Hello everyone,

According to documentation this device supports 32kb data/instruction cache. But actually we are running on default 4kb size.

I am unable to find clear information on how to change the size of the cache. I tried manipulating the cache size override register but without success.

Is there any application note on the subject, or can you please advise me on how or where I can find documentation to do it?

Thank you.

over 4 years ago

0 Sunil Oak over 4 years ago

TI__Mastermind 49120 points

The cache size is configured to be 32KB. See below snapshot of the Cache Size ID Register (CCSIDR):

See the register description and bitfield definition in ARM's Cortex R5F reference manual:

0 Zakaria Nakrachi over 4 years ago in reply to Sunil Oak

Prodigy 130 points

Thank you Sunil,

I am confused about these registers. CCSIDR tells me that it is a 32Kb cache, but the cache size override register (CSOR) is set to zero which means the size is 4Kb ?

Thank you

0 Sunil Oak over 4 years ago in reply to Zakaria Nakrachi

TI__Mastermind 49120 points

Per ARM's documentation, the cache size override register is a write-only register. So you can configure the override register and then read from the CCSIDR register for the cache size configured.

0 Zakaria Nakrachi over 4 years ago in reply to Sunil Oak

Prodigy 130 points

thank you very much, I was doubting that lauterbach wasn't reporting the right value of COSR but I wasn't sure.

Thank you for clearing this out

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LC4357: Changing cache size