Hercules™ Safety Microcontrollers

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Hercules™ Safety Microcontrollers

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Related Posts

  • Forum Post: Re: CCMR4 self-test

    Vaclav Cechticky
    Hi Prathap, I was running the CCM Self Test for several months without any problem, in non-debug mode. I just observed strange degradation of the whole test sequence. First failed the Error Forcing Test, now also the Self Test and also Self Test Error Forcing Test. I'm still investigating the...
    on Mar 28, 2012

  • Forum Post: Re: CCMR4 self-test

    Vaclav Cechticky
    Hi Prathap, I just found the bug in my code. I apologize for confusion and thank you for help. Regards Vaclav
    on Mar 28, 2012

  • Forum Post: CCMR4 self-test

    Vaclav Cechticky
    Hello, I have suddenly difficulties to reproduce results of the CCMR4 self-test. The 8th bit for the CCM-R4F status register (CCMSR) is not set, which would mean that the self-test is not completed. I've updated my code with newly generated code base from HalCoGen 3.00.01, which shouldn't...
    on Mar 27, 2012

  • Forum Post: Re: TMS570 FIQ Interrupts with CCMR4 error

    Jean-Marc Mifsud
    Bruce, The way the CCMR4 works, doesn't allow debug mode. Will it be possible in your case to run your code, without stopping the CPU? In other words, can you set a break point in your ISR, run your code and will the CPU is running, assert a nRST to force the device to restart from reset. ...
    on Apr 16, 2012

  • Forum Post: RE: CPU Compare Module mismatch error on Hercules TMS570LS31x HDK

    Jean-Marc Mifsud
    Zeeshan, Because of the lockstep implementation, it is necessary to initialize all the CPU registers. If you are using HalCoGen, this initialization is done in the startup code. On Cortex R4F only the CPSR_SVC and PC registers have a defined state after reset. All others registers (Including the...
    on Jun 5, 2012

  • Forum Post: RE: Which Self Check mode of CCM-R4 does bit 16 of CCMSR Register is SET?

    Jean-Marc Mifsud
    Pashan, Your question has been forwarded to our CCMR4 expert. He will be back to you shortly.
    on Sep 11, 2012

  • Forum Post: RE: Which Self Check mode of CCM-R4 does bit 16 of CCMSR Register is SET?

    Jean-Marc Mifsud
    Pashan, Bit 16 of CCMSR (CMPE) is set on the following conditions: 1] An compare error happens in normal mode (lockstep) while CPU is running, or 2] CCMR4 is in self test error forcing mode and CPU is running. In debug mode, self test error forcing mode does not set bit 16. A system reset or...
    on Sep 12, 2012

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