Hercules™ Safety Microcontrollers

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Hercules™ Safety Microcontrollers

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ESM
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  • Forum Post: How are error conditions handled?

    S Tsuei
    The various error conditions on the device are managed by the Error Signaling Module (ESM). The severity level of the error determines how the error is handled. The severity level is device specific and is implemented by mapping each of the device error signals to the appropriate group of error/interrupt...
    on Mar 10, 2010

  • Forum Post: Parity check for ADC

    Vaclav Cechticky
    Hello, I'm trying reproduce/re-run available tests which are creating and verifying parity errors for ADC1 and ADC2 on RM48 HDK. Whereas other provided parity tests are working in a predictable way, the parity checks for ADC1,2 are sometimes passed, one is failed or both failed. I guess...
    on Feb 8, 2012

  • Forum Post: TMS570 TCRAMW Redundant Address Decode Logic Test

    Nathaniel Schlossberg
    Hi, I have been trying to use the TCRAM wrapper test mechanism to verify behavior of the redundant address decode and compare logic. I have run into some confusing results. To start off, I make sure to clear the appropriate registers like RAMUERRADDR, RAMERRSTATUS, set a test address in RAMADDRDECVECT...
    on Mar 29, 2012

  • Forum Post: Intermittent Data Abort Exception

    Tony Morrell
    Intermittent Data Abort Exception Hi, CCS 5.1.0.201201061800 CGT 4.7.1 TMS570LS31x Hercules Microcontroller Development Kit (HDK) Spectrum Digital XDS510 USB Plus I have an intermittent data abort exception occuring on the above platform, as follows: 1. Reliably after power on reset (S4 PORRST...
    on Jul 25, 2012

  • Forum Post: eFuse Controller autoload error and ESM Module Group 3 Errors

    Christian Herget
    Hello, the TRM says that all erros in ESM Group 3 are CPU Aborts. I assume, that Data Aborts and Prefetch Aborts will be generated by Uncorrectable ECC Faults. But what about the ESM Channel 3.1Error (eFuse Controller autoload error), does this also generate an CPU abort and if so which one? ...
    on Aug 23, 2012

  • Forum Post: Uncorrectable flash ECC error from a RTI irq not involving flash on a RM48HDK

    Tim Mulder
    Hi, I'm using the RM48HDK dev. kit with HALcoGEN generated code. When the RTI generates an irq (compare0), ESM.Stat3 becomes 0x00000080. Often, ESM.Stat1 becomes 0x00000040, but not always. The nError pin is driven low and the nError LED is turned on. It clearly occurs when the interrupt is fired...
    on Nov 6, 2012

  • Forum Post: (Again) ESM after Startup

    dominik schuierer
    Hi I´ve read http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/107810.aspx which describes exactly what i ran into: I get an ESM Stat 1 of "0x80000000 immediatly after startup. I set the STCCLKDIV to 3 (using 140 Mhz System clock), but the error remains. Even more: After resetting...
    on Nov 16, 2012

  • Forum Post: RE: nERROR pin and ESM Low-Time Counter Preload Register

    Prathap
    Hi 1) Sorry for the confusion, It's a typo in the TRM, ESMLTCPR and ESMLTCR default value at reset = 0x3FFF. I will report this to the corresponding team. 2) Suggestion for your Used case a) Writing "esmREG->KEY = 0xAU;" will take the Error Pin Low immediately. Leave ESMLTCPR default...
    on Mar 20, 2013

  • Forum Post: "FMCBUS2 Error Check" code generated by HALCoGen (03.05.00)

    Yusuke Nomoto
    Hello, I have a trouble for "FMCBUS2 Error Check" code generated by HALCoGen (03.05.00) on TMS570LS3137. Boot sequence stops under following conditions. Could you teach me wheter it is correct behavior? 1. "FMCBUS2 Error Check" is enabled by checking "SAFETY INIT"...
    on May 1, 2013

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