Hercules™ Safety Microcontrollers

Forum Post: RE: Problem using FTCA interrupt

Scott Green — Sun, 26 May 2013 00:29:00 GMT

Zhaohong,

I noticed the latest release of HalCoGen 03.05.01 fixed my first issue by now automatically generating the ISR and associated pragma calls so that the FTCA interrupt works correctly. Thank you.

Regarding the use of DMA with SPI2, I reviewed the SPI_DMA example that you provided and distilled it into the enclosed example that runs on the TMS570 USB dev kit to illustrate the issue that I am observing. With FLAG_POLLED=1 and NUM_TX=64, the code successfully executes a polled TX/RX of 64 bytes on SPI2.

However, when FLAG_POLLED=0, the code illustrates that a DMA TX/RX of the same 64bytes on SPI2 is erratic. Only 17 bytes are seen on the MOSI line, and they occur in 6 bursts of 2-3 bytes each. If the RX DMA is disabled, then the SPI2 MOSI line shows a 5.4usec burst outputting 11 bytes, but not the full 64bytes. The DMA is writing 64bytes to the SPI2 DAT1 register, but the SPI2 is not reliably transferring the data out the MOSI line.

When NUM_TX=1, the DMA TX/RX with SPI2 works. This indicates that the code setup is correct, but it only works for a single byte transfer which is better done directly to the registers rather than using DMA. When NUM_TX=2, the SPI2 MOSI line shows that both bytes are transmitted, but the received data is just the last byte repeated twice.

My interpretation of these results is that SPI2 works in a polled mode, but has a memory access conflict when using DMA. Does anyone have a work-around or an example that enables the use of DMA on SPI2?

Thank you for your time.

Scott

Forum Post: RE: emac receive only broadcast packets - RM4 HDK

Tomasz Chalupka — Sat, 25 May 2013 16:35:00 GMT

Hi,

sorry for my impatience but have You any idea what I can do about my problem? I'm also looking forward to this tutorial 'cause something less complex than LwIP demo would be helpfull.

Regards,

Tomasz

Forum Post: RE: Good way to check stack size

KARTHIKEYAN RAJAMANICKAM — Sat, 25 May 2013 15:02:00 GMT

Hello,

There is no inbuilt hardware mechanism in ARM core to do this, I can suggest a few ways to do this.

a. If you are interested in abort, then you can configure the memory which you think should not be used by CPU due to over growing stack as separate MPU region.

b. Assign the AP property of that region to No Access, so whenever stack overgrows in to this region you will get an abort.

a. The more simpler way should be to assign the stack size lot more than what you will need and fill them using a known pattern prior to the run.

b. Run your test and make sure the max stack usage scenarios like nested routines, interrupts etc are occurring.

c. At the end you can check the memory to see whats the last entry which contains something not matching the known pattern should be the max stack utilization number.

Hope this helps.

Best Regards,

karthik.

Forum Post: RE: HET Interrupt

KARTHIKEYAN RAJAMANICKAM — Sat, 25 May 2013 14:38:00 GMT

Hello Chafik,

Thanks for updating. I will go ahead and close this thread.

Best Regards,

Karthik.

Forum Post: RE: How to sync ePWM1 using N2HET1_LOOP_Sync in champion

Sunil Oak — Fri, 24 May 2013 19:58:00 GMT

Hi Keyur,

See my comments below:

question 1: How does clearing PINMMR36[24] pin would affect, because I see only pin PINMMR36[25] select the N2HET1_LOOP_SYNC line.

>> You are right. PINMMR36[24] has no impact on the selection. You only need to set PINMMR36[25] to allow N2HET1_LOOP_SYNC to be used as ePWM1_SYNCI.

question 2: Currently I am using N2HET1 and N2HET2 for different functions and already N2HET2 is select as master, so Is that possible to have both Master ?.

>> A master/slave configuration is only required if the timer modules need to all be synchronized (have the same time base). If the two N2HET modules operate independent of each other, then the master/slave configuration has no effect.

>> One feature of the N2HET module is that it forwards the EXT_LOOP_SYNC out on the N2HET1_LOOP_SYNC when the N2HET1 module is configured to be a slave. This will allow you to even use the N2HET2 to be the master time-base genarator.

question 3: would you clarify for about "2 VCLK4 Pulse Strength block" ? if I have LR=128, HR=1, so LR clock would be = 128*VCLK2, so this means every 128*VCLK2 + 2 VCLK4, N2HET1 send trigger to ePWM ? what clock frequency VCLK4 block taking in here ?

>> The loop-resolution clock frequency is defined by the HR and LR prescalers. As per your configuration, the LR clock period is 128 * VCLK2 period. This LR clock as well as the LOOP_SYNC signal (output by the N2HET module) are not 50% duty cycle clock signals. Rather, there is a high-phase that is 1 VCLK2 period wide, followed by a low-phase that is 127 VCLK2 periods wide.

>> The ePWM modules operate using the VCLK4 clock domain. There is no dependency between VCLK2 and VCLK4 clock ratios, other than they are both divided down from the HCLK clock domain. This requires the design to stretch the N2HET1_LOOP_SYNC signal to at least 2 VCLK4 periods to ensure that the LOOP_SYNC signal is latched inside the ePWM1 module.

question 4: Is that possible to set trigger ePWM when counter value in N2HET1 reach without burning external pin ?

>> This is not supported, as the LOOP_SYNC signal is in phase with the LR clock. The N2HET1[16] is multiplexed with the ePWM1_SYNCI function, so whatever you output on N2HET1[16] can be used as a synchronization input by the ePWM1 without any external connections. This is another option that is available, but does require you to actually output the sync signal on the pin.

Regards,

Sunil

Forum Post: RE: What is the RM48L952 recommended ADC input voltage range?

Sunil Oak — Fri, 24 May 2013 18:25:00 GMT

Jason,

The offset errors being discussed in the referred app note are in the order of +/- 60 counts and hence require frequent periodic calibration or trimming! The Hercules MCUs have a max specified offset error of +/- 3 counts without any calibration.

These errors are small enough to still have the full input voltage range available for the application.

Regards, Sunil

Forum Post: RE: eFuse Controller autoload error and ESM Module Group 3 Errors

KGreb — Fri, 24 May 2013 13:50:00 GMT

Manoj,

Please reference SPNU499A, Chapter 32. The information was not in earlier versions of the TRM.

Regards,
Karl

Forum Post: RE: Where do I get Flash API Version 1.60 for F021?

John Hall — Fri, 24 May 2013 12:19:00 GMT

Hello Pashan,

There is no F021 Flash API v1.60. The version you are referencing in the screen shot is the version of the wrapper library used in Flash470 and UniFlash.

Forum Post: RE: The maximum error of MibADC on TMS570LS2125

Yusuke Nomoto — Fri, 24 May 2013 11:34:00 GMT

Hello,

You said "The ADC total error specified in the datasheet is actually the error you can expect without any calibration."
So, I want to know the ADC total error after calibration by using either the 4-point or the mid-point calibration sequence.
Could you determine?

Best Regards

Nomoto

Forum Post: RE: Lauterbach TRACE32 peripheral files (.PER)

Jean-Marie Voisin — Fri, 24 May 2013 09:46:00 GMT

Hello all,

Any news from the TI representative ?

I can't even see the CPU registers.

Could you please provide the .per files in a visible way?

Are they available somewhere?

Thanks in advance, JM

Forum Post: RE: DMA interrupts

Jack Andrews — Fri, 24 May 2013 09:27:00 GMT

Thanks. Also, for anyone else struggling, don't forget to include #pragma INTERRUPT(isrFucntion, IRQ) for all your ISRs! Also, this document is useful for explaining how it all works:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363g/BEIDDFBB.html

Forum Post: RE: Reading Analog Input Values

ishan maniar — Fri, 24 May 2013 07:44:00 GMT

Hey,

I want to get the value of the analog input, and then may b send that value over a CAN message,

or toggle some output depending on the input value.

Regards,

Ishan Maniar

Forum Post: RE: ESM Group 3 error

Charles Johnston — Thu, 23 May 2013 18:32:00 GMT

Hi Sunil,

That was it. The SW change we made just happened to cause a prefetch from an unused and uninitialized flash location. I filled flash by editing sys_link.cmd:

FLASH0 (RX) : origin=0x00000020 length=0x0017FFE0 fill=0xEEFF3300

FLASH1 (RX) : origin=0x00180000 length=0x00180000 fill=0xEEFF3300

The problem now is that a debug load takes 10 minutes instead of 15 seconds. We will be disabling ECC for SW development unless you have a better solution.

Thanks for your time.

Charlie Johnston

Forum Post: RE: TMS570 - Flashing of OTP with nowFlash fails

John Hall — Thu, 23 May 2013 17:20:00 GMT

Hello Pashan,

These libraries will be updated after the release of v2.0.0 of the F021 Flash API. I believe this means it will make it into the next version of UniFlash after v2.2.

Forum Post: RE: Starting up a new project with lwIP and TMS570

KARTHIKEYAN RAJAMANICKAM — Thu, 23 May 2013 15:53:00 GMT

Hello Matteo,

Will forward your query to our Ethernet experts.

Best Regards,

Karthik.

Forum Post: RE: mibspiREG3 FMT0 clock polarity inverts data not clock

KARTHIKEYAN RAJAMANICKAM — Thu, 23 May 2013 15:45:00 GMT

No problems ! It happens all the time.

Will close this post.

Best Regards,

Karthik.

Forum Post: RE: MibSPI rx DMA

Zhaohong Zhang — Thu, 23 May 2013 15:27:00 GMT

Srikanta,

You need to check the CCS memory map configuration to make sure that Flash is set to address 0x0. When you load the code, you should see CCS message about the process such as 'flash is being erased".

Thanks and regards,

Zhaohong

Forum Post: RE: What is the Flash API Function call for Flash Compaction within F021 Flash API?

John Hall — Thu, 23 May 2013 14:38:00 GMT

Hello Pashan,

Compaction could not be easily removed from the flow in Flash470 so it calls a null function that does not do anything when compaction is selected on F021 devices.

Forum Post: RE: Interrupts during flash write

KGreb — Thu, 23 May 2013 13:41:00 GMT

Hi Tony,

The FIQ limitation is introduced by the ARM v7R architecture as implemented by ARM in Cortex R4. FIQ is not part of hardware vectoring so that it can be directly accessed for use as an NMI with fastest possible response. Typically, this is an advantage, but in this case it causes an issue. As you noted, there are two alternatives already supported in the device architecture - swapping the SRAM and flash so that the SRAM is mapped at 0x0 to manage the vector table or use IRQs with vectoring instead of FIQ.

Best Regards,
Karl

Forum Post: RE: Accessing DMA working registers - Current Transfer Count Register (CTCOUNT)

J Joson — Wed, 22 May 2013 21:51:00 GMT

Thanks Sunil for the TIP. When I have another active dma channnel, the working registers are updated upon arbitration. Thanks again.