Hercules™ Safety Microcontrollers

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Hercules™ Safety Microcontrollers

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DMA
Related Posts

  • Forum Post: Complex SPI, DMA, CRC, RTI, FIQ integration scenario

    Tony Morrell
    I have a complex TMS570 SPI problem which I would appreciate some advice on. Requirements: My SPI Master transmits a 9-word (i.e. 9*16=144-bit) message. The first 8 words contain control data, the last word contains a CRC of the 8 data words. I am using one transfer group within my SPI, and only...
    on Apr 4, 2011

  • Forum Post: Automatic SPI DMA on SPI message receipt

    Tony Morrell
    Hi, I am having trouble setting up an automatic DMA to RAM on completion of SPI frame reception. I have looked at examples from other forum posts but am not making any progress. I have DMA working for a software driven event, activated from the SPI interrupt service routine by setting the appropriate...
    on Apr 7, 2011

  • Forum Post: SPI receive complete to triggered DMA transfer large delay

    Tony Morrell
    Hi, I have an issue with DMA time to service from request which I hope someone can help me with. I have an SPI receive transfer which I am using to trigger a DMA transfer of received data into a RAM buffer. On DMA frame transfer complete interrupt I activate a 'service routine'. By driving...
    on Apr 13, 2011

  • Forum Post: SPI Receive RXRAM all-zero without XDS510 connected

    Tony Morrell
    Hi, I have an interaction problem between use of XDS510 USB debugger, TMS570 MCU Development Kit, SPI and DMA modules. My setup is two TMS570 MCU connected by SPI1 to SPI1, CS, CLK, SOMI and SIMO, running at 8MHz. My SPI Master controls transmissions of 9*16-bit frames every 62.4us. The SPI Master...
    on Apr 26, 2011

  • Forum Post: TMS570 DMA and DCAN Hardware Request

    Joris Gansler
    Hello, I'm trying to configure DCAN and DMA to move incoming messages from the IF3-Registers to an address in RAM. Therefore I connected DCAN1 (with MessageBox1 as TxD) and DCAN2 (with MessageBox1 as RxD) and set the Update Enable Bit for the DCAN2-MsgBox1. To enable DMA Request for DCAN2IF3 I set...
    on May 6, 2011

  • Forum Post: DMA and MCRC Timing

    Tony Morrell
    Hi, A simple question for you. If I use a DMA to stream data into MCRC channel 1 and from that first DMA chain a second DMA to stream data into MCRC channel 2, can it be guaranteed that MCRC channel 1 compression complete interrupt will always occur before MCRC channel 2 compression complete interrupt...
    on May 17, 2011

  • Forum Post: TMS570: ADC + DMA

    Jason Bell
    Hello, I'm using a TMS570LS20216SPGE on the TMDX570LS20SUSB development stick. I am attempting to configure an A/DC and a DMA channel to work together to store a continuous A/D sample stream into a RAM circular buffer without core intervention. I have set up one A/DC group to run in continuous...
    on Jun 27, 2011

  • Forum Post: Re: TMS570: ADC + DMA

    A Arora
    Jason, this is being looked into and we plan to have a response shortly. Regards, Abhishek
    on Jun 28, 2011

  • Forum Post: Documentation bug for DMAPCR PARITY_ENA

    Andrew Schultz
    Hello, I think there is a documentation bug in table 16-66 in the description of the PARITY_ENA field. It says initially that 5h will disable the parity check (this is the default value, so I am guessing this is correct), and all other values will enable parity checking. Then, there is a note that...
    on Feb 1, 2012

  • Forum Post: Re: Documentation bug for DMAPCR PARITY_ENA

    Pratip Kumar
    Hi Andrew, I had a look into this and I'm consulting with the concerned design expert. Will let you know of the status soon. Regards. Pratip
    on Feb 2, 2012

  • Forum Post: DMA problem

    Greg_
    After enabling DMA the corresponding bit in the CNTRL register remains zero (DMA disabled) What clock drives the DMA ? I double checked my Clock mappinh and all clocks are enables Any ideas ?
    on Aug 16, 2012

  • Forum Post: RE: DMA. nonAuto-Initiation.

    Jean-Marc Mifsud
    Sergey, I've forwarded your question to our DMA expert. He should be back to you shortly.
    on Sep 10, 2012

  • Forum Post: DMA and Interrupts

    Maxime Brunelle
    Hi, I'm using a TMS570 running with Micrium µC/OS-III. I have written a DMA driver which currently works well except for one detail: the interrupts stay in a pending state. When testing with DMA channel 0, I've enabled bit 0 of register FTCINTENAS (FTC Interrupt Enable Set) and of register...
    on Sep 26, 2012

  • Forum Post: Does DMA BERA Interrupt occur during DMA Write Cycle to Flash Address Space?

    Pashan None
    Hello Support, Assume that Flash Configuration is same as Power On Default, that mean it is READ-ONLY mode. I was expecting to have DMA BERA interrupt when DMA Write Cycle destination is Flash Address Space. I see completion of DMA Write Cycle with DMA BTCA Interrupt instead of DMA BERA Interrupt...
    on Oct 7, 2012

  • Forum Post: Need help on CRC module

    Tim Park
    Hi experts, Could you please help to provide a CRC module example based on F021 chips(such as TMS570LS3137,RM4x) through AUTO Mode, Semi-CPU Mode and Full CPU Mode, to prove they can get the same correct calculated signature? And I cann't run the codes at the link:http://e2e.ti.com/support/microcontrollers...
    on Oct 11, 2012

  • Forum Post: DMA

    Sergey3
    For formation of short signals on an output of port of general purpose I used the DMA module in a mode of block transmission. Serial transmission of data array to port was made for testing of working capacity { 0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1 }. The following pattern was as a result watched approximately...
    on Oct 16, 2012

  • Forum Post: TMS570LS20216 DMA parity check

    Chuck Wong
    Hi there, I configured DMA channel 15 to accept request from line #13 for RTI event1 that is happening every 60 seconds, using DMA Port B to perform transfer data from the on-MCU Flash ROM to the CRC module for 64-bit CRC check, for a total of 2 MB ROM - 1024 bytes. The DMA module is configured with...
    on Feb 21, 2013

  • Forum Post: Efficient data transfer with MibSPI and DMA

    Yusuke Nomoto
    Hi, I'm using TMDX570LS31USB (TMS570LS3137 is implemented), and I want to transfer TG0 and TG1 data with MibSPI and DMA. In ideal, once MibSPI and DMA setting are finished, no ARM processing is needed. I've programmed in hope of working above processing, however it doesn't work well....
    on Apr 30, 2013

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