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Hercules™ Safety Microcontrollers

Welcome to the Hercules™ Safety Microcontrollers Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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NHET
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Related Posts
  • Forum Post: Re: TMS 470 HET instruction set help

    Prathap Prathap
    Hi Thanks for posting your query, but this is the forum mainly for TMS570 microcontrollers. TMS470 HET module and TMS570 NHET module are slightly different. However the below explanations are applicable for both TMS470 HET and TMS570 NHET modules. --> Conditional Address defines...
    on Mar 19, 2010
  • Forum Post: HET IDE - User's Guide v1.0 - "Running a demo"

    Jeff Stafford Jeff Stafford
    Using the HET IDE and following the User's Guide v1.0 "Running a demo", the Assemble and Load step produces the following output in the IDE: Info: (I804) /IEEE_Std_1666/deprecated: deprecated function: sc_get_default_time_unit Warning: Unable to load document het.vcd WARNING: Default...
    on May 1, 2010
  • Forum Post: TMS570LS Technical Reference - NHET - ECMP Instruction Description

    Jeff Stafford Jeff Stafford
    Reading the NHET chapter of the TMS570LS Technical Reference, the ECMP instruction has the following description: If the hr_lr bit is cleared, the pin action will occur after a high resolution delay from the next resolution clock. What is meant by the phrase "next resolution clock"...
    on May 1, 2010
  • Forum Post: Re: HET IDE does not correctly import settings for input timer channels from vcd file

    alain boutin alain boutin
    What is the HET IDE ? Where can i find that ? Is it from TI or a third party ?
    on May 17, 2010
  • Forum Post: NHET pin disable output

    Tim Martin Tim Martin
    I want to enable and disable (force to high-impedance) individual NHET output pins. I was originally going to hold pin nDIS low, and then use register HETPINDIS to enable and disable output pins. I understand now that holding pin nDIS low will also force HETGCR.HETPINENA low, which will disable ALL...
    on Aug 16, 2010
  • Forum Post: NHET Parity RAM write access by CPU when TEST Bit is set and PARITY_ENA=0x05 or 0x0A

    Pashan Pashan
    Hello, Please answer below each question separately. 1> Is it possible to write 1-Bit data or 32-Bit Data to Parity RAM Area of NHET from CPU side when the HETPCR Register have TEST Bit set and PARITY_ENA=0x05? 2> Is it possible to write 1-Bit data or 32-Bit Data to Parity RAM Area of...
    on Aug 28, 2010
  • Forum Post: Unable to find NHET RAM 64-Bit Write Access feature within TRM

    Pashan Pashan
    Hello, In the "spnu199d.pdf" document for TMS470R1VF3382 device HET, there is 64-Bit HET RAM Write Access feature. Reference within spnu199d.pdf document is as shown below: 4.1.3 CPU Access to Timer-RAM I am trying to find 64-Bit NHET RAM Write Access within spnu489a.pdf. ...
    on Oct 21, 2010
  • Forum Post: NHET RAM and registers acting as "Write Only" ... ?

    Richard G Richard G
    I'm experienced with the (N)HET, but I'm starting a new project on a TMS570LS20216 and creating a new driver from scratch. I am able to load a small PWM output program to NHET RAM, configure the NHET registers, start the program running, and continue to modify the registers/RAM while running...
    on Nov 19, 2010
  • Forum Post: Dead time configuration of TMS570.

    wang jianchao wang jianchao
    I want to use TMS570 to control PMSM, but there is no hardware TIMER used to generate SVPWM just like TMS320 series, we have to design using NHET. I have designed software to generate SVPWM by NHET, but I'd like to know some details of Dead time. For example if the dead time is longer than the...
    on Jan 10, 2011
  • Forum Post: NHET used for data output

    Fred P Fred P
    I have an unusual usage for NHET module: I want to use it as a semi independant transfert port. Since it runs parallel to the core and can be fed RAM data by the HTU, it can greatly offload the CPU. However I foresee this limitation: MCMP, ECMP, SHFT all seem to allow resolving of only one pin state...
    on Feb 16, 2011
  • Forum Post: Re: NHET "Trip Zone"

    Sunil Oak Sunil Oak
    Hello Jean, The TMS570 NHET module has an input that allows you to do just this. The GIOA[0] pin input connection is connected to the NHET pin disable input as well as to the GIO module. This connection is defined on page 21 of the TMS570LS20216 datasheet. There is also a register inside the NHET...
    on Mar 2, 2011
  • Forum Post: The number of pwm in TMS570

    Thomas Song Thomas Song
    A customer is considering TMS570 MCU for On Board Charger application in HEV. I could not find the terminology for PWM in TMS570 MCU. Could you tell me which peripheral is for PWM generation in TMS570? or Could you recommend the MCU for OBC application? Best regards, Thomas Song
    on Mar 7, 2011
  • Forum Post: Re: The number of pwm in TMS570

    Frank Noha Frank Noha
    Hello Thomas, the NHET module is a programmable timer and theoretically it can generate as many PWMs as NHET pins are available. However in an application, it depends also on if the PWMs should have different frequencies, on the available NHET memory and the complexity of the program (e.g. synchronous...
    on Mar 7, 2011
  • Forum Post: NHET PCNT Instruction

    Dave Saggs Dave Saggs
    Hi, I am using the TMS570 Microcontroller Development Stick, with a TMS570LS20216 MCU (ASPGEQQ1). I have a short NHET program to measure time periods: P01 PCNT { next=P02,reqnum=0,request=GENREQ,irq=ON,type=FALL2FALL,pin=10,period=0,data=0,hr_data=0} P02 BR {next=P01,cond_addr=P01,event=NOCOND}...
    on Mar 8, 2011
  • Forum Post: TMS570 Development Kit from TI

    J��rn Rieve J��rn Rieve
    I have two questions. First :. I have initialized the CPU with: systemREG1->PLLCTL1 = 0x00000000U | 0x20000000U | (3U << 24U) | 0x00000000U | (5U << 16U) | (149U << 8U); systemREG1->VCLK2R = 0U; systemREG1->VCLKR = 0U; so the CPU is running with 100 MHz and...
    on Jun 1, 2011
  • Forum Post: Re: TMS570 Development Kit from TI

    Pratip Kumar Pratip Kumar
    Hi, Regarding your first question, how are you measuring the VCLK2 ? Your second question has been forwarded to out HET expert -Pratip
    on Jun 3, 2011
  • Forum Post: Re: NHET Loop back mode in HET Simulator

    Gerhard Wenderlein Gerhard Wenderlein
    yes you can connect nHET[0] with nHET[1] by wire on the board if you take care about the pin input and output settings. hetREG->DIR = 0xFFFFFFF1U; // pin0:output, pin1:input But in your NHET program you need two CNT instructions: L00 which allows to set the period of your test PWM on pin...
    on Jul 22, 2011
  • Forum Post: Re: NHET pins as GPIO

    Christian Herget Christian Herget
    Hi Jut, as Sunil already said, the NHET module has speacial registers to use the port as GIO and no NHET program is necessary to use them as GIO. If you are using HalCoGen, you can use the GIO drivers of HalCoGen for this purpose. The following Code will set the HET pin 0..5 as output, and than...
    on Oct 4, 2011
  • Forum Post: Re: NHET module usage

    Bindu Tanguturi Bindu Tanguturi
    Thanks for the reply. Can you please elabarate on what is LRP and HRP ? Suppose i need to measure the input singal (square wave frequecy varies from 10 to 15mhz). And My pheriperal clock is at 80Mhz. So how to select the values of hr and lr prescalars ? . My main program may run at the 50ms...
    on Oct 10, 2011
  • Forum Post: NHET generating wrong PWM frequency?

    Marco Moreno Marco Moreno
    Hi, I'm using HALCoGen to setup a simple PWM output and am having problems getting the output frequency correct. My requirement is 460.8kHz 50% duty cycle. Some other system parameters are: HCLK = VCLK = VCLK2 = 64MHz hetREG->PFR->LRPFC = 4 hetREG->PFR->HRPFC = 0 ...
    on Oct 19, 2011
  • Forum Post: hetGetTimestamp always returns 0

    Kevin Spharler Kevin Spharler
    What are the pre-requisites for using the HET's timestamp function? I've tried all kinds of things but I have yet to get hetGetTimestamp to return anything but 0 to me. Thanks, --Kevin
    on Dec 13, 2011
  • Forum Post: AND / XOR-shared HR Structure

    Matthias Siegenthaler Matthias Siegenthaler
    Hello all The output stage of N2HET allows to combine two consecutive outputs to achieve a higher timer resolution or a symmetrical PWM. When working with pulses instead of set/clear for the two combined outputs, two inputs of the XOR/AND-gate change at the same time. (End of Program loop) Is the...
    on Feb 7, 2012
  • Forum Post: HTU from CPU to N2HET

    Matthias Siegenthaler Matthias Siegenthaler
    Hi all I’m sentenced to implement a IO-driver for a Hercules Microcontroller. I want to use N2HET (TMS570LS3137) to generate some PWM-Signals. Some of the outputs belong together, some are independent, but all of them handle high resolution and XORing of outputs and everything must be managed...
    on Feb 14, 2012
  • Forum Post: N2HET protect program field

    Matthias Siegenthaler Matthias Siegenthaler
    Hi all Document SPNU499 on page 946 in the description of PPF: How do I have to understand the term < program fields > in the description of PPF-Bit? N2HET-RAM contains the N2HET-program wherein one Instruction is a combination of PF +CF+DF(+RES). Does it mean, that PF can be protected...
    on Feb 16, 2012
  • Forum Post: Re: N2HET protect program field

    Jean-Marc Mifsud Jean-Marc Mifsud
    Matthias, This is correct. When the NHET is running and PPF bit is set, the Program Field is protected against write access. (of course, read are still possible) In this mode, all master are still able to write to Control and Data field. Best Regards, Jean-Marc
    on Feb 17, 2012
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