First of all, I would like to thank all the champs in this TI forum. I have learnt a lot of things by reading through the forum discussions on MSP430.
My problem is as follows :
I am setting up MSP430F5438A (in the EXP430 board) as an SPI master with a sensor attached to its P10 as the slave. I have changed the MCLK frequency to 16MHz using the "Init_FLL_xx" (HAL_UCS.h and HAL_UCS.c) function available from the UserExperience code example. My assumption is that the SMCLK would also be 16MHz (--am I right here?).
The following would be my code for initializing the P10.x on the EXP430 board for SPI (Master) with SMCLK as the source clock. I am using the USCI A3 module.
//pin config#define SPI_STE_PIN BIT7#define SPI_SIMO_PIN BIT4#define SPI_SOMI_PIN BIT5#define SPI_CLK_PIN BIT0
//spi init code
P10OUT |= SPI_STE_PIN;
P10SEL &= ~SPI_STE_PIN;
P10DIR |= SPI_STE_PIN;P10SEL |= (SPI_SIMO_PIN + SPI_CLK_PIN + SPI_SOMI_PIN);UCA3CTL1 = UCSWRST;UCA3CTL0 = UCMST + UCSYNC + UCMSB + UCCKPL;UCA3CTL1 |= UCSSEL__SMCLK;UCA3BR0 = baudrate; //example baudrate I tried was 16 (decimal) so that UCxCLK would be 1MHzUCA3BR1 = (baudrate >> 8);UCA3MCTL = 0;UCA3CTL1 &= ~UCSWRST;
for(i=0;i<2;i++) __delay_cycles(16 * 100); //let the state machine get some time to settle
I have an SPI analzser and a sensor which I have connected to the pins from the MSP430 port. I started analyzing
the waveform and found that I am not able to see any clock in the display even if the MOSI is
spitting the data out (0x44 was the data). From one of the forum posts, I tried to continuously
read and write through the SPI lines and found that only at very low frequencies
(when I give baudrate = 1000) I am able to see proper clock pulses in the UI. The analyzer supports
upto 50MHz and I am sampling the lines at the highest rate possible.
Please find the image below for the same :
I think something very trivial is missing and I have played around with different SPI configurations,
but none to succeed (just for seeing the clock pulses at SPI_CLK >= 1MHz). I feel there could be
a small configuration or setting which I have not done. Please reply back if you have faced
the same issue/have pointers to solve the same.
Thanks a lot,
The setup seems to be okay, and the fact that you're seeing a clock pulse on a low baudrate, it also seems to indicate that things are okay from teh software side.
However, not seeing pulses on high baudrate but on low one seems to indicate sort of a capacitive shortcut. The analyzer doesn't show the waveform of the signal, obnly whetehr the voltage crosses its high threshold. With a digital scope you might see that the pulses are there but attenuated and not rectangular. Check your PCB for capacitances or shortcuts on the clock pin.
_____________________________________Before posting bug reports or ask for help, do at least quick scan over this article. It applies to any kind of problem reporting. On any forum. And/or look here.If you cannot discuss your problem in the public, feel free to start a private conversation: click on my name and then 'start conversation'. But please do so only if you really cannot do it in a public thread, as I usually read all threads. And I prefer to answer where others can profit from it (or contribute to it) too.
Hi Jens-Michael Gross,
Thanks a lot for your comments.. I will surely check the capacitive short.
One thing I did was to do the same software settings on another port (P3 , USCI B0 module) and I got the clock perfectly. So I am continuing now with B0 module itself.
I am now getting some "spike" like reply from the slave during a read cycle. The SPI slave reply does not go with the clock which the master has provided (data shift edge is correct, but the signal dies off before the data sample edge. PL=1, PH=0 setting for SPI). This makes the master receive only zeros. (Please take a look in the attached image, MOSI line is written with 0x00 for pulling out the data from MISO).
Have you ever come across such a situation? Can you point me to some directions for this problem?
Thanks for all your posts. They are very informative.
This is indeed weird. It looks like an electrical problem. Again, a logic analyzer only showes the moment where a level exceeds the threshold voltage. It does not show the real voltage on these pins. Normally, the slave should output its bit a short moment after the clock is going low, while the master fetches it when the clock is going high. In case of a 0xff response, the signal input on MISO should be a flat high line from the first falling edge of the clock.
Are you really sure that you have the correct wiring? I could imagine such kind of response if the clock were accidentally connected to the CS (chip select) pin, so the falling edge of the clock actually enables the slave (causing a short spike on MISO)Do you have GND connected? Else you have a 'floating' GND, which moves depending on the signals. And the analyzer (and the MSP) only sees the resulting beat frequency, cut to its threshold voltage.
The CS and CLK pins were not connected directly, but there was a problem whenever I connected the analyzer to my setup.
I have removed the analyzer and the SPI interface seems to work (by observing the RXBUF in the debugger). The problems which I posted being in the hardware, it would have been much harder to track without the replies.
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