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MSP430G2553 PWM and UART clock issue

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Posted by Tommy Romano

on Apr 13 2012 09:24 AM

Hello All -
Disclaimer: I am new to this, so please be gentle.

Object of my code: To drive two independent PWM signals, that will each drive a different LED light. AND be able to received RS323 UART commands from a PC. The commands from the PC will change the values of TA1CCR1 and TA1CCR2, thus changing the brightness of the LEDs.

The code for the LED PWM driver and the UART tx/rx are from sample code provided by TI documentation. Independantly, the LED PWM code works fine. And I have been successful in sending a single CHAR via RS232 UART to the uC and have seen it respond (TX) back on my oscilliscope.

However, when I combine the two pieces of code into one program, I can not get the uC to respond (TX) to the sent (RX) CHAR from the PC. After some trial and error, I think I narrowed it down to that the PWMs are being driven by the SMCLK, and the UART by the ACLK, and the uC doesn't like this.??? Any pointers on how to configure the clocks correctly, to enable this to work? (note: I do have a crystal on xin/xout pins). Help is much appriciated. (Code embedded below)
-Tommy

_______________________

#include <msp430g2553.h>

char string1[8];
char i;
char j = 0;

int redPWMval=255;
int bluePWMval=255;

void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Kill WDT

    P1DIR = 0xFF;         // All P1.x outputs
      P1OUT = 0;         // All P1.x reset
P2DIR = 0xFF;         // All P2.x outputs
P2OUT = 0;         // All P2.x reset
P1SEL = BIT1 + BIT2;         // P1.1 = RXD, P1.2=TXD
P1SEL2 = BIT1 + BIT2;         // P1.1 = RXD, P1.2=TXD
P2DIR = BIT2 + BIT5;                           // P2.2 and P2.5 output
P2SEL = BIT2 + BIT5;                        // P2.2 and P2.5 options select

     TA1CCR0 = 256;                                    // PWM period
TA1CCTL1 = OUTMOD_6;                // CCR2 reset/set
TA1CCR1 = redPWMval;                     //CCR1 PWM duty cycle

TA1CCTL2 = OUTMOD_6; // CCR2 reset/set
TA1CCR2 = bluePWMval; //CCR2 PWM duty cycle

      TA1CTL = TASSEL_2 + MC_1 + TACLR;         // SMCLK, up mode, clear TAR

      UCA0CTL1 |= UCSSEL_1;         // CLK = ACLK
      UCA0BR0 = 0x03;         // 32kHz/9600 = 3.41
UCA0BR1 = 0x00;
UCA0MCTL = UCBRS1 + UCBRS0;         //Modulation UCBRSx = 3
UCA0CTL1 &= ~UCSWRST;         //**Initialize USCI state machine**
IE2 |= UCA0RXIE;         // Enable USCI_A0 RX interrupt

__bis_SR_register(LPM1 + GIE);             // Enter LPM1, interrupts enabled
}

// USCI A0/B0 Transmit ISR
#pragma vector=USCIAB0TX_VECTOR
__interrupt void USCI0TX_ISR(void)
{
UCA0TXBUF = string1[i++]; // TX next character

if (i == sizeof string1) // TX over?
IE2 &= ~UCA0TXIE; // Disable USCI_A0 TX interrupt
}

// USCI A0/B0 Receive ISR
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR(void)
{
string1[j++] = UCA0RXBUF;
if (j > sizeof string1 - 1)
{
i = 0;
j = 0;
IE2 |= UCA0TXIE; // Enable USCI_A0 TX interrupt
UCA0TXBUF = string1[i++];
}
}

All Replies

Posted by Leo Hendrawan

on Apr 13 2012 10:19 AM

Mastermind27025 points

Hi Tommy,

if you look at the following table which can be found in the 2xx UG:

Using 32 kHz ACLK for 9600 baud rate will gives you around 20% maximum TX and RX error. My guess is that by combining the two codes you mentioned above, the CPU becomes more busy, and therefore increases even the error rate.

I would go with sourcing the USCI module with 1MHz calibrated value of SMCLK which according to the table will give you very low TX, RX error probability. You can easily use the calibrated value of the clock registers by applygin the following small code at the beginning of your code:

BCSCTL1 = CALBC1_1MHZ;

DCOCTL = CALDCO_1MHZ;

FYI, the register value above is not really hard to be calculated manually. I wrote a small guide before about calculating the USCI baud rate at the following wiki page:

http://processors.wiki.ti.com/index.php/USCI_UART_Baud_Rate_Gen_Mode_Selection#Calculating_The_USCI_UART_Baud_Rate_Register_Values

I hope this helps.

-Leo-

Regards,

Leo Hendrawan

- Now that my signature has caught your attention, please click the "Verify Answer" button if this post answers your question. Thanks! -

Posted by Tommy Romano

on Apr 13 2012 10:39 AM

Prodigy60 points

Leo-

Let me make sure I understand your answer. Which I'll try later today when i get back into the lab.

I should add these two lines to my main():

BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;

AND, change the following lines too, based on your wiki page;

      UCA0CTL1 |= UCSSEL_2;                    // Chagned from CLK = ACLK, to CLK = SMCLK
      UCA0BR0 = 0x68;          // changed from 0x03 -> 32kHz/9600 = 3 :: to 0x68 1MHz/9600 = 104
      UCA0BR1 = 0x01;                                   // changed from 0x00 to 0x01

if that is true, do I still need the 32khz crystal osc. on xin/xout pins? I wouldn't think i do.

Thank you.

Posted by Leo Hendrawan

on Apr 13 2012 14:16 PM

Mastermind27025 points

Hi Tommy,

actually, it should be like this:

void main(void)

{

BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ;

...........

UCA0CTL1 |= UCWRST;

UCA0CTL1 |= UCSSEL__SMCLK;    // CLK = ACLK
UCA0BR0 = 104;          // 1MHz9600 = 3.41
UCA0BR1 = 0x00;
UCA0MCTL = UCBRS0;         // Modulation UCBRSx = 1
UCA0CTL1 &= ~UCSWRST;         //**Initialize USCI state machine**
IE2 |= UCA0RXIE;         // Enable USCI_A0 RX interrupt

..................

}

Hope this helps.

-Leo-

Regards,

Leo Hendrawan

- Now that my signature has caught your attention, please click the "Verify Answer" button if this post answers your question. Thanks! -

Posted by Jens-Michael Gross

on Apr 16 2012 10:52 AM

Guru139900 points

lhend
My guess is that by combining the two codes you mentioned above, the CPU becomes more busy, and therefore increases even the error rate.

Since the USCI is a hardware UART, the PCU load does not have any influence. In fact, a higher CPU load that doesn't allow filling TXBUF in time, would cause a more stable (but not much) sending, since the additional idle time between two sent bytes would allows for better resynchronization. This effect, if it applies at all - depending on the other side - sould be negligible.

What I can imagine is that the additonal PWM output causes ripples on VCC (if there is a significant load on this pin) or crosstalk. If the UART connection is already shakey (due to the high clock error rate on 32kHz crystal), this can make things worse.
It is even possibel that the PWM signal influences the crystal.

_____________________________________
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Posted by Tommy Romano

on Apr 17 2012 09:08 AM

Verified Answer

Verified by Tommy Romano

Prodigy60 points

Leo & Jens-Michael -

Thank you for the assistance. I was successful in getting the UART and the PWM control working at the same time. By changing the code as Leo suggested, (found some typos in his code, see corrected syntax in green). I also removed the crystal completely and used only the SMCLK (for both the UART and PWM) from the internal Master clock and DCO set to 1MHz..

UCA0CTL1 |= UCSWRST;
UCA0CTL1 |= UCSSEL_2; // CLK = SMCLK

It still wasn't performing correctly, so I rechecked my circuit and found I had some issues with my wiring of the MAX232. Which incidently operates best at 5V, and I am running the MSP430 at 3.3V. I found the MAX3232, which does the same as the MAX232 only at 3.3V. Once I fixed this, I was able to send messages from my PC, through the USB/Serial port to the uC and get a response echo back from it, and change the PWM value via this route.

Another thing to note. The sample code for the UART puts the uC into LPM3. which disables the SMCLK, MCLK and DCO, so I changed it to LMP1 since I changed from using the ACLK to the SMCLK.

I am off and running.
Thank you.

Tommy