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Why is Nop added after bis_sr_register instruction

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Posted by Aamir Ali

on Apr 16 2012 04:25 AM

Expert2115 points

I have seen some codes,

nop is added after bis & written in comments- set breakpoint here.

I also noted that as soon as bis instruction is executed, debugger first goes to next instrucion & then go to ISR.

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Posted by mark sonnentag

on Apr 16 2012 06:19 AM

Expert1890 points

Hi,

some MSP430 have an hardware bug that could corrupt the SP/PC if there was no NOP after the BIS instruction. This problem is described for example in the CC430 errata as CPU24, CPU25 and CPU26 bug.

Posted by Jens-Michael Gross

on Apr 16 2012 12:02 PM

Guru141810 points

Aamir Ali
I also noted that as soon as bis instruction is executed, debugger first goes to next instrucion & then go to ISR.

All MSP instructions that have a target that is a processor register (like SR/R2 for GIE bit) do not require access to the memory bus while the write operation is performed. So this cycle is used to fetch the next instruction.
If this instruction has a breakpoitn on it, the breakpoint is triggered at the instruciton fetch, not at the instruciton execution (which follows at least one clock cycle later).
This causes the breakpoint behind an instruction that sets GIE (with pending interrupts) to be hit before the ISR is executed. Same applies for entering LPM. The breakpoint right after the instruction that sets LPM is hit before LPM is entered.
If you clear GIE, you should also add a NOP after this. As it may happen on some older MSPs (I think this has been fixed on the newer ones) that the isntruciton right behind is fetched and an interrupt is granted at the same time. Causing the isntruciton to be executed first and the interrupt then, which probably isn't the intention of clearing GIE :) However, by clearing GIE a bit earlier before the operation that must be uninterrupted, will make the NOP obsolete in this case - it can well be a useful operation.

So if you want to set a breakpoint after a bis instruciton that enables GIE or LPM, put a NOP behind it and place a breakpoint on the next, real instruction.This ensures that the breakpoint is hit after LPM has ended and/or the ISR has been executed.

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