I am trying to verify that if I choose to use 3-pin SPI (Master) mode on the USCI ports on the MSP430F5436A device, that I can independently configure the USCxxSTE (Tx enable) pins as a stand-alone chip select or essentially a GPIO pin? Can anyone confirm this statement?
Yes, your statement is accurate. I do exactly that.
Terry Jendon99319I am trying to verify that if I choose to use 3-pin SPI (Master) mode on the USCI ports on the MSP430F5436A device, that I can independently configure the USCxxSTE (Tx enable) pins as a stand-alone chip select or essentially a GPIO pin?
Note that STE and CS are two different things, even in 4-wire mode. If you use STE, it will only control the port pin drivers. You'll still have to detect it as CS signal and reset the SPI hardware (byte sync) and the high-level protocol of your application. It is therefore a good idea to use a P1 or P2 pin with interrupt capability for an incoming CS signal if you are slave.
In master mode (except if you are in a multi-master environment), STE is completely meaningless. And the generation of a CS signal is completely under software control (GPIO), as there might be any number of CS signals for multiple slaves, all on the same SPI bus.
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Thank you for your response. I will be using the SPI interface in 3-pin SPI (single) master mode only. Therefore, the STE as you said will be meaningless in my application.
Therefore, based on your feedback it sounds like since the STE pin function will not be used, I should be able to generate the CS via software control using it as a GPIO.
Terry Jendon99319I should be able to generate the CS via software control using it as a GPIO.
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