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TI Home » TI E2E Community » Support Forums » Microcontrollers » MSP430™ Microcontrollers » MSP430 Ultra-Low Power 16-bit Microcontroller Forum » USCI_Ax or USCI_Bx ports on MSP430F5436A devices
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    USCI_Ax or USCI_Bx ports on MSP430F5436A devices

    This question is not answered
    Terry Jendon99319
    Posted by Terry Jendon99319
    on May 11 2012 13:49 PM
    Intellectual325 points

    Hello all;

    I am trying to verify that if I choose to use 3-pin SPI (Master) mode on the USCI ports on the MSP430F5436A device, that I can independently configure the USCxxSTE (Tx enable) pins as a stand-alone chip select or essentially a GPIO pin?  Can anyone confirm this statement?

    Thanks

    Terry

    USCI_Ax USCI_Ax MSP430F543xA
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    • Jeff Tenney
      Posted by Jeff Tenney
      on May 11 2012 18:34 PM
      Guru10795 points

      Yes, your statement is accurate.  I do exactly that.

      Jeff

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    • Jens-Michael Gross
      Posted by Jens-Michael Gross
      on May 15 2012 09:05 AM
      Guru140085 points

      Terry Jendon99319
      I am trying to verify that if I choose to use 3-pin SPI (Master) mode on the USCI ports on the MSP430F5436A device, that I can independently configure the USCxxSTE (Tx enable) pins as a stand-alone chip select or essentially a GPIO pin?

      Well, STE is STE. It is used or not. But you can simply not select the STE function fo this pin and use it as CS signal by normal GPIO means.

      Note that STE and CS are two different things, even in 4-wire mode. If you use STE, it will only control the port pin drivers. You'll still have to detect it as CS signal and reset the SPI hardware (byte sync) and the high-level protocol of your application. It is therefore a good idea to use a P1 or P2 pin with interrupt capability for an incoming CS signal if you are slave.

      In master mode (except if you are in a multi-master environment), STE is completely meaningless. And the generation of a CS signal is completely under software control (GPIO), as there might be any number of CS signals for multiple slaves, all on the same SPI bus.

      _____________________________________
      Before posting bug reports or ask for help, do at least quick scan over this article. It applies to any kind of problem reporting. On any forum. And/or look here.
      If you cannot discuss your problem in the public, feel free to start a private conversation: click on my name and then 'start conversation'. But please do so only if you really cannot do it in a public thread, as I usually read all threads. And I prefer to answer where others can profit from it (or contribute to it) too.

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    • Terry Jendon99319
      Posted by Terry Jendon99319
      on May 15 2012 09:57 AM
      Intellectual325 points

      Hello Jens-michael;

      Thank you for your response.  I will be using the SPI interface in 3-pin SPI (single) master mode only.  Therefore, the STE as you said will be meaningless in my application. 

      Therefore, based on your feedback it sounds like since the STE pin function will not be used, I should be able to generate the CS via software control using it as a GPIO. 

      Thanks

      Terry

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    • Jens-Michael Gross
      Posted by Jens-Michael Gross
      on May 15 2012 13:53 PM
      Guru140085 points

      Terry Jendon99319
      I should be able to generate the CS via software control using it as a GPIO. 

      Exactly. As you could do with any other GPIO pin (maybe a different one allows for easier layout)

      _____________________________________
      Before posting bug reports or ask for help, do at least quick scan over this article. It applies to any kind of problem reporting. On any forum. And/or look here.
      If you cannot discuss your problem in the public, feel free to start a private conversation: click on my name and then 'start conversation'. But please do so only if you really cannot do it in a public thread, as I usually read all threads. And I prefer to answer where others can profit from it (or contribute to it) too.

      Report Abuse
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      You have posted to a forum that requires a moderator to approve posts before they are publicly available.
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