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Can the SPI of MSP430F5328 run with a 25MHz clock?
I use the MSP-TS430RGC64B EVM board. I want to estimate the max SPI speed of MSP430F5328.I choose the USCI_A0 as SPI Master，and USCI_A1 as SPI slave.and i use Dupont line to connect the used pins.I configure XT2 (25MHz clock) as SPI clock,and devide 1.here is my spi intialize source code.
GPIO_setAsPeripheralModuleFunctionOutputPin(__MSP430_BASEADDRESS_PORT3_R__, GPIO_PORT_P3, GPIO_PIN3 ); GPIO_setAsPeripheralModuleFunctionInputPin(__MSP430_BASEADDRESS_PORT3_R__, GPIO_PORT_P3, GPIO_PIN4 ); GPIO_setAsPeripheralModuleFunctionOutputPin(__MSP430_BASEADDRESS_PORT2_R__, GPIO_PORT_P2, GPIO_PIN7 );
ret = SPI_masterInit(__MSP430_BASEADDRESS_USCI_A0__, SPI_CLOCKSOURCE_SMCLK, 25000000, SPICLK, SPI_LSB_FIRST, SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, SPI_CLOCKPOLARITY_INACTIVITY_HIGH);
GPIO_PORT_P4, GPIO_PIN4 ); GPIO_setAsPeripheralModuleFunctionInputPin(__MSP430_BASEADDRESS_PORT4_R__, GPIO_PORT_P4, GPIO_PIN5 ); GPIO_setAsPeripheralModuleFunctionInputPin(__MSP430_BASEADDRESS_PORT4_R__, GPIO_PORT_P4, GPIO_PIN0 );
ret = SPI_slaveInit(__MSP430_BASEADDRESS_USCI_A1__, SPI_LSB_FIRST, SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, SPI_CLOCKPOLARITY_INACTIVITY_HIGH );
SPI_enableInterrupt(__MSP430_BASEADDRESS_USCI_A1__, SPI_RECEIVE_INTERRUPT );
I have set the core voltage level as 3.if SPICLK = 12500000 ,Master's transmitting and receiving data is correct. But if SPICLK = 25000000 ,Master's transmitting data is correct while recieving data has a shift error. if Master transmits 0x66, slave gets 0xCC. Can MSP430F5328's spi can run with a 25Mhz clock? or what i configure is wrong?
I want to estimate the max SPI speed of MSP430F5328.
I want to estimate the max SPI speed of MSP430F5328.
Here's how to calculate the max. SPI speed that your applictaion is capable of: 1) From the MSP430 (master) data sheet record the Tvalid,mo and Tsu,mi 2) For the MSP430 (slave), record the Tsu,si and Tvalid,so 3) The max bit rate is calculated as: Fmax = 1/ [2* max ( Tvalid,mo(msp430-master) + Tsu,si(msp430-slave) OR Tsu,mi(msp430-master) + Tvalid,so(msp430-slave))] Assuming both master and slave are 430s this works out to more than 7 Mbps (using MSP430F5328). For the USCI module, the max SPI bit clock is BRCLK, so you will need to use a clock source of >3MHz for the SPI clock to achieve this data rate. Also I would recommend running MCLK at a higher frequency, keeping Vcc at 3V, PMMVCORE = 3, and using DMA to move bytes into the TX Buffer (ensuring that the SPI transmit interrupt flags are not subject to interrupt priority/latency). The good news is that the USCI is capable of back-to-back SPI transfers, meaning you can load the SPI TXBUF with a byte while the previous byte is being moved onto the bus. All this being said, it is important to understand the system and how SPI is prioritized when compared to other application tasks.
Felix76837transmitting data is correct while recieving data has a shift error.
first, the phase or clock polarity can be mismatched. Assuming identiucal setup on both sides (both an USCI MSP), thsi shouldn't be an issue.
The othe rproblem is lack of synchronization.
SPI is a bitstream. There is no strt or stop bit synchronizing the byte borders. This synchronization is done by the chip select line (do not confuse this with the STE signal). By pullign the CS pin low (this is a software controlled GPIO operation on both sides) the slave knows that the master is ready to start a transfer. The slave then has to ensure that it is ready to receive. Also, when CS goes high, the transfer ended, no matter where it stands now. THis can be mid-byte. The slave msu thten reset its SPI controller, so the next CS low starts with a fresh new byte.
If this isn't handled properly, the slave may erraneously take the port pin initialization of the master for a clock signal and already latch-in the first bit. And all following bits are then one bit off.
So the master pulls CS low, the slave detects this and then clears the SWRST bit of the USCI. And when CS goes high, the slave will detect this too and set SWRST.
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