I'm currently trying to interface with a MSP430F5510 using 4-wire JTAG. The chip that is interfacing with it is a FPGA, though functionally my goal is to have it look no different than any other chip that attempts to program the MSP over JTAG.
The problem I'm currently having is getting the MSP to enter JTAG mode at all. According to the documentation in SLAU320e, the correct entry sequence should be what is shown here (again, using the 4-wire JTAG sequence option):
I am having the FPGA generate a waveform which looks like this (the top signal is TEST/SBWTCK and the bottom is ~RST/NMI/SBWTDIO:
and am getting no results. Now, I realize the issue could be either the entry sequence, the TAP reset sequence, or the IR_SHIFT which should shift out the JTAG ID. I began with debugging the entry sequence first, since without that being correct, the other two would naturally not work. In debugging this, I attached a MEP-FET430UIF USB programmer to the MSP in the 4-wire JTAG configuration shown in the documentation for that part, which is what I have been using to successfully program the chip thus far. I hooked a scope up to the TEST/SBWTCK and ~RST/NMI/SBWTDIO lines to see what entry sequence the FET was using, and obtained the following waveform (the yellow line is TEST/SBWTCK and the blue line is ~RST/NMI/SBWTDIO):
Now, this doesn't match either the 2-wire or the 4-wire JTAG entry sequences shown in the documentation. My questions are as follows:
First, does the FET use a different entry sequence than a normal chip would use to enter JTAG mode?
Second, assuming I am using the correct entry sequence with the FPGA, is there a recommended minimum length of time that each pulse should hold between transitions? The only thing the documentation says is that to exit JTAG mode, TEST needs to be held low for at least 100 us, so I am assuming the entry sequence should hold it low for less time than that. Also, I found another post stating that TEST should only be pulsed low for less than 15 us, though I do not know if that is in regards to this specific chip or another chip.
Third, is there a good way to tell whether the entry sequence has succeeded without using IR_SHIFT to shift out the JTAG ID? In other words, I'd like to know if my first step has succeeded before moving on to debug the next two steps.
Thanks in advance to anyone with information regarding this! Once again, the fact that I'm interfacing from an FPGA should not fundamentally matter, because I can replicate any waveform and timing. I just need to know /what/ waveform and timing to replicate.
SLAU320 may have some useful information for you. It talks about how to use the 2 and 4 wire JTAG interfaces to program memory on the MSP430.
Multitech Systems Inc
Thanks for the information! However, I have already referenced SLAU320 (it's where I got what TI stated should be the entry sequence for JTAG)
I think this is where your problem lies:
Devices with SBW also support the standard 4-wire interface. The 4-wire JTAG interface access is enabled by pulling the SBWTDIO line low and then applying a clock on SBWTCK. Exit the 4-wire JTAG mode by holding the TEST/SBWTCK low for more than 100 μs.
So your signal on SBWTCK needs to be less than 100 uS otherwise you are just exiting JTAG mode. Page 11 of SLAU320 says that the SBWTCK low must be less than 7 uS or it drops out of SBW mode. So maybe the low needs to be <7 uS for turning on JTAG mode also.
One thing to note about the Scope plot of the debugger output. You are at 50 mS per division. That is awful slow. Maybe the digital scope is aliasing the actual signals so they look slower?
There is also this not on page 21 of SLAU320 :
On some Spy-Bi-Wire capable MSP430 devices, TEST/SBWTCK is very sensitive to rising signal edges that can cause the test logic to enter a state where an entry sequence (either 2-wire or 4-wire) is not recognized correctly and JTAG access stays disabled. Unintentional edges on SBWTCK can occur when the JTAG connector is connected to the target device. There are two possibilities to work around this problem and ensure a stable JTAG access initialization:
• Actively drive SBWTCK low before powering up the device or while plugging in the connector to avoid unintentional rising signal edges.
• Run the initialization sequence multiple times (two to three repeats are typically sufficient to establish a stable connection)
Maybe your part is one of the sensitive ones?
Thank you! Yes, I think that is part of the problem.
Another part of the problem is this: when I send the JTAG mode entry sequence, the chip appears to operate normally, unless actually sending, receiving, or processing JTAG commands. Should this be the case? Even if I hold the chip in reset, it seems to operate as it normally would after running the entry sequence. This seems like it would invite a great many problems and undesirable chip operation especially if JTAG were being used to write program code into the chip's flash memory, as I would like to do.
Since the JTAG interface can be used to debug the processor, that fact that it is running is not suprising. I bet you need to send JTAG commands to the processor to halt it and open access to the memory bus before you can program memory.
I believe you are correct. That is what I am attempting to do, to take control of the processor using JTAG.
To that end, I am attempting to run this sequence:
However, on the step "Bit 9 of TDO Word = 1", this never happens. In fact, any time I do a DR_SHIFT sequence, the only thing that is returned is what I shifted in (so x1501 is returned after the first shift, then x0000 is returned)
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