Can anyone help me in correcting the below code for continuous mode PWM generation with varying duty cycle from 25%, 50%, 75%, frequency can be anything.
The below code is not varying the PWM period. so please let me know what should be OUTMOD configuration and CCR1 value.
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
P1SEL |= 0x40;
P1DIR |= 0x40; // P1.0 output
CCTL1 = OUTMOD_7;
TACTL = TASSEL_2 + MC_2 + ID_3 ; // SMCLK, contmode
CCR1 += 50;
But since you're running the timer in cont mode (MC_2), it counts from 0 to 65535.Assuming 1MHz for SMCLK, one timer tick is 1µs.Firs tloop TA1 should be on for 50µs, off for 65485µs (~0.1% duty cycle).Next ti will be the same as you have a wait for 100k cycles while the next timer loop begins after 65536 cycles. Third cycle will be with 0.2% duty cycle and so on.
Instead of doing a wait for 100k cycles, you should rather look for TAIFG bit in TACTL1. If it is set, a timer overrun has occured (one cycle has passed) and you can go for the next step. Then manually clear the TAIFG bit!
However, with the timer in cont mode, it takes 655 cycles = 43s to reach 50% duty cycle with a stepsize of 50. With your code, it will take ~66s.
Well, you don't write which MSP you use, so I cannot check whether you're using the right output pin at all :)
P.s: with the current setup, PWM frequency is 15.26Hz
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