MSP430AFE253 24-bit ADC - Is it possible to stream ADC samples/data out of pins 17-20 using SDxDO pin functions?

Oh, this feature is implemented and documented. However, it isn't what you might think.

Look at the datasheet, port pin schematics. The data outs are activated setting all three P1DIR.x, P1SEL.x and P1SEL2.x bits.

However, I don't know what one wants with this data stream. It is NOT a streamed version of teh conversion results, it is internal the Delta-Sigma comparator output. The bitrate is one bit per SD24 clock. And you need to do digital filtering on your own.

If you apply a low-pass filter on it, you'll get a scaled version of the input signal (scaled by the ratio of port pin output voltage to selected SD24 reference). And if you collect the bits, you'll have to collect 65536 bits for a 16 bit result.

Since it is a simple output stream of the internal comparator, there is nothing to do except enabling the output. The bits only depend on the reference voltage and the conversion clock frequency.

Thanks for the quick response!  I think what my customer is trying to do is to use the 24-bit ADC in the MSP430AFE253 almost as a "stand-alone" 24-bit ADC to do continuous sampling of their analog signal(s).  The idea is then to pass that information (the 24-bit ADC samples) back to a second MSP430 that will be doing all the heavy lifting of computational analysis and system operation.  So the question my customer is getting at is this: how fast can we get 24-bit ADC samples out of the 24-bit ADC in the MSP430AFE253 and pass those to another MSP430? 

That leads me to one follow-on question for you: is this datastream from the 24-bit ADC documented in more detail somewhere that I can point my customer to?  I guess I'm not following why these pin-out functions were enabled if it's a useless bit stream.  My customer may be ok with doing their own analysis of the bitstream - but they would need to know more details (i.e. things that you mention like the need to collect 65536 bits for a 16-bit result) about this bit stream to make the determination about whether it's something they want to attempt or not.  Again, thanks so much for your help!

Kevin Ross said:

  The idea is then to pass that information (the 24-bit ADC samples) back to a second MSP430

How fast depends on the OSR ratio and the communication between the two MSPs.

With 1MHz conversion clock and OSR=32, the SD24 can generate 31250 samples per second. But 24 bit doesn't really make sense with an OSR of 32. If MCLK runs on, say, 8MHz, you have 256 clock cycles for doing the transfer (assuming only one SD24 and no channel switching). Far enough for sending 3 bytes using SPI. Impossible with I2C. And almost impossible with UART (requires very tight assembly coding).

For higher OSRs, precision rises and conversion rate drops, relaxing things a bit (or several bits :) )

However, (to quote a variant of one of my favorite poems):

You can get cheap, fast and precise ADCs.
Cheap and fast ones are not precise,
cheap and precise once are not fast,
fast and precise ones are not cheap,
cheap, fast and precise ones are not possible.

Kevin Ross said:

is this datastream from the 24-bit ADC documented in more detail somewhere that I can point my customer to?

I don't know of any info from TI. However, the SD24 is described as a 2nd order Delta-Sigma converter. So the general description of a 2nd order Delta-Sigma will show you what this bitstream likely is.
Personally, I don't know how this particular 2nd order works (my description above was about 1st order, I never dealt with 2nd order hardware on low level, I only know that it exists).
I only know that it incorporates a secondary delta/sigma stage before the output quantizer, and the quantizer uses an additional random noise quantization level shift, which allows for easier digital filtering with higher precision. I never dug through the math.

You can find some info here and here.

Kevin Ross said:

i.e. things that you mention like the need to collect 65536 bits for a 16-bit result

Well, this is the simplest-of-all digital filter. If you implement a low-pass over the bitstream (counting each '1' bit as Vref+, each '0' bit as VRef-) you'll get an analog result that pretty much fits the 'real thing' after much less bits, since a low-pass recognizes the pattern in the bitstream rather than just the count.
See, 32  '1' bits in a row indicate VRef+, 32 '0' bits indicate VRef-. 16 '1' and 16 '0' bits in a 32 bit block indicate (VRef+-VREF-)/2. But there is much redundancy. 16 '1' followed by 16 '0' will give the same result as a chain of intermittent '1' and '0' bits. And the result only has a resolution of 5 bits. Putting a low-pass over the bitstream will give you a fractional result depending on the order the bits come. So you have after 32 btis a result with higher resolution, or the same 6 bit result after less bits. This is what the SD24 digital filter does.
It does, however, require that the input signal frequency is lower than the filters cutoff frequency, while the plain counting method always gives the correct (moving, if you use a FIFO) average over the counted interval.

I know what that raw data stream is and how I want to use it, but need the polarities and relative phase of clock (SDCLK) and data (SDxDO) from the SD24_A. Neither the MSP430AFE2xx data sheet nor the F2xx users guide documents those details. Searching on SDCLK, SDxDO and SD1DO got me to this thread but turned up nothing else relevant. If I were at my home location I could grab an oscilloscope and measure, but I am working remotely just now.

Can anyone tell me where to find a depiction of those waveforms?

A partial answer to my own question is: the SDxDO data changes on the positive SDCLK clock transition. Therefore set whatever is looking at data to sample on the negative transition of the clock. If you are listening with the on-board USART in SPI slave mode, then CKPH = CKPL, and you can use either 1 or 0 (as needed to choose behavior when STE changes) so long as both are the same. I chose zero.

I still don't have access to an oscilloscope today but I do have a target board and some chips. I wrote a program in the AFE233 to copy successive values of P1IN (which watches the P1 pin states even when they are selected for clock or data output)  into a byte array using a tight loop taking 11 processor cycles, ran the processor at 12MHz MCLK and ran the SD24 at 125KHz. That gave me at least eight samples per SDCLK cycle so I could see the clock and data states change by looking at the resulting array contents with a debugger.

TI normally uses true logic unless there is a long-established contrary standard, like RST*, so it is a good bet that they do so here for the data line, but I did not try to verify that just now.

I'd still like to see specifications, but I have what I need to know for now, and perhaps it's enough to be useful to someone else.

Phil Ekstrom said:

I'd still like to see specifications, but I have what I need to know for now, and perhaps it's enough to be useful to someone else

 I don't figure what is targeted this strange idea.. AFE is targeted to energy measurement so its DSP extract from voltage and current phase rms value apparent active and reactive power plus harmonic analysis and PF as distortion rate plus phase shift.

 Extracting raw data from delta sigma stream and process on another MSP sound so crappy... Why not use a Delta Sigma from GP series?? Or why not use a DSP instead if decimation or different filter needed? Processing power and instruction are different on DSP and is more and more simple to realize filtering.

Roberto,

Your puzzlement is not surprising - I have not said in the postings above what I plan to do, but I will say it now.

Others appear to want to use the SD24 for its originally intended purpose, perhaps adding additional filtering, etc. applied to the raw bit stream, which would be possible, or looking for serial output after filtering, which is not available from the SD24. I have a different goal: randomly generating numbers.

I have an application note attached to another thread "SD16 as a random number generator"about randomly generating high-entropy bytes at a rate of 4 per millisecond using an SD converter. Experiments show that units which pass other tests first to weed out bad units will pass the NIST battery of tests for random byte generators, so this approach yields a convenient high-quality generator. That can be valuable and we have used this approach to make up a batch of USB "Entropy Keys" for internal use. Still, that generation rate is slower than would be useful in some applications, so I am looking at the SD24 which due to its raw bit-stream output would seem able to run more than ten times as fast, despite having the same clock rate and general structure as the SD16.

The key idea in both applications is to select input 7 (shorted input normally used for offset measurement), select maximum gain of nominally 32, and harvest the contact noise (also called  kT/C noise, which is thermal) of the input switch and comparator block. In normal SD converter operation, the filter is used to chase that noise down into the lower bits of the output register, where it is usually ignored. In the SD16 work I set LSBACC to get at the low order bits and for an OSR >= 256 I find that the lowest byte is (in most units of the SD16) almost completely random. Details including some theory and rationale are in the app note, which I commend to you.

The SD24 gives additional direct access to the stream of comparator decisions. Under the same conditions of measuring an actual zero input that stream should be nearly random also once the converter has had time to settle. I was getting ready to read out the stream and test it for correlations, bit statistics, etc.

That's what I am up to - it is not to use the SD converter for its originally intended purpose at all, but to make positive use of the randomness that the designers have worked hard to throw away. There is a saying "One man's noise is another man's data" and I suppose that applies here. So my plan may still be strange, but perhaps not so distressing once I explain it.

You will have to ask others what it is that they are up to. I do note that increasingly TI SD converters allow for raw bit-stream output and even input, so one may infer customer interest, which is likely based on some kind of good sense - presumably related to custom filtering.

Phil Ekstrom

The approach seems interesting, but I think there is a wrong consideration:
" Under the same conditions of measuring an actual zero input that stream should be nearly random"
No, on a near-zero result, the stream is mostly zero. Only when the zero results sum up to VCC in the integrator stage, there is one '1' comparator bit. You may measure the distance between individual '1' bits in the data stream, which should be fairly random.
To get a random output stream, the noise must be shifted to Vref/2.
Well, in bipolar mode, this should be 0V. But then there is the input offset, which is additionally boosted by the gain and any offsets inside the PGA. It will cause the resulting bit stream to be less random than you think (even though after digital filtering, the LSBs would be still random)
IMHO it would be better to use a real input pair and apply some adjustment to trim the offset to zero. E.g. a poti between the two inputs with the wiper connected to AVSS. It will also increase noise :)

The SD24_A uses differential inputs.

The datasheet says:

Input A7 is a shorted connection between the + and – input pair and can be used to calibrate the offset of the SD24_A input stage.

So the result won't be exactly centered at zero, but with 24 bits, there is more than enough noise anyway.

What you say (mostly zero comparator decisions with zero input) would be true for a zeroth order modulator that averaged instead of integrating its feedback, but for one with an integrator in it, I think we expect that once the fed-back integrator output has settled to match a constant input, we would ideally get alternating 1 and 0 decisions to keep the integrator from walking away from the settled condition. Ideally we would get alternating 1 and 0, but actually a random stream (with a probability of 1/2 but a deficiency of long runs because of the feedback) since that situation is dominated by contact noise. There is reason to keep the ADC input voltage away from the edges of the input range because the converter does not work as well near the edges, but as you noted zero is at the center of a bipolar input range so is ideally placed. That is why I always use a bipolar input range and shorted input terminals when harvesting noise. Yes, not at the exact center because of comparator input offset but once the integrators settle, the offset will be gone from the decision stream, though not from the filter output that remembers how it got there in its own integrators.

When I harvest noise from filter output, I ordinarily subtract successive output values to remove the offset. Truncating the output to a field narrow enough to flatten the distribution also removes the correlations which you would otherwise get when using successive values and using each value in two subtractions. Details of all that are in the app note uploaded to the SD16 thread.

I have a MSP-TS430PW24 target board with an MSP430AFE253 in it wired up to feed SD24 comparator output into SIMO and the SD24 data clock into the SPI clock pin. The real answer will be to study that bit stream - which I mean to do but have not found time to pursue yet.

Phil Ekstrom said:

What you say (mostly zero comparator decisions with zero input) would be true for a zeroth order modulator that averaged instead of integrating its feedback,

Ah, no.
It depends on whether you have a clocked or unclocked comparator feedback.
On a delta-sigma (as someone once said, only the river sigma can have a "sigma delta"), there is always an integrator (sigma). Higher order just increase the number of integration stages before the final comparator, to move the quantization noise further up the frequency band.

In the delta stage, the feedback (0V or Vref) is subtracted from the input signal. Then it is integrated. And the integrated voltage is compared against the reference.

If you do not clock the feedback (directly subtracting the comparator output form the integrator input), the comparator begins to oscillate as soon as the integrator has reached the reference voltage. The duty cycle of the oscillation depends on the input signal, and if you 'capture' the comparator output at a certain frequency, this will lead to a noisy output influenced by the feedback loop speed and the comparator output sampling frequency.

This method is used if the absolute value is less important compared to the noise. e.g. in bandwidth-limited signal transmissions.

If you clock the feedback, which is the more common approach, the comparator output is latched with the same clock signal that takes the samples. As a result, the feedback is 0 or 1 for a fixed period of time. If e.g. the input signal is 10% of Vref, the output will be 10 times '0'. then the integrated input will cross the comparator threshold. As a result, the next bit sampled will be '1' and at the same time, Vref will be subtracted from the input before integrating. Which leads to integrating a signal of -90% Vref. The next 9 bits will be zero again. Then one '1', 9 '0' end so on.
The smaller the input voltage, the higher the number of zeroes before a single '1'.

Now since 0V will be in the middle of a bipolar input stage, one could assume an average stream of 0 and 1. But it could be as well that just the polarity of the differential input is taken to generate the sign of the result, and the absolute value is taken as input to the converter. The MSP has no negative supply, so the inputs use a method to 'shift' this value based on the selected input range (0V..Vref or +-1/2Vref)

Since the exact implementation of the converter is unknown (as well as the implementation of the digital filter), I don't know what will actually happen. The meaning of the DS16 digital output stream is not really explained. Yes, it is the comparator output. But what does the comparator output actually mean? It is the output of an unknown circuitry before it goes into another unknown filter to produce a known result.

BTW: There is a difference between averaging and averaging. For an Delta-Sigma (without digital filter), you need a moving average over 2^n data bits for n bit result precision. For an input exactly in the middle of the input range, 2 bits would be enough, but not at the upper and lower edges.
For the 0th order modulator you cited, you'd need to average all results since beginning of time. You subtract the zeros and add the ones from your maximum count.
A little bit (but inverse) like the method used by VOC files for compressed digital audio output on the good old Soundblaster cards (never won a significant market share, uncompressed WAV won, as it could be simply put on a cheap DAC, an 'advanced' music system introduced by Microsoft long time ago, I think it was called 'Windows Sound System' and was barely more than a parallel port with a resistor ladder and an amplifier.)

Yes, I assumed a clocked comparator, and there seems no reason to think otherwise. I think we don't disagree about what happens when a delta-sigma (often called SD, as in SD24...) converter is operating at the center of its range, whether it is measuring 0V in a bipolar mode or Vref/2 in a unipolar one: A converter with only quantization noise would generate alternating 1 and 0.We don't need to know very much about the particular implementation to conclude that.

With a real switched-capacitor modulator, there is also thermal contact noise (also called kT/C noise) at the switched capacitive input and that will tend to randomize the 1 and 0 stream without changing the long term proportions of half and half. In this line of converters, the apparent resolution of the comparator is finer than the calculated kT/C noise, so I expect that the stream will be quite random. The bottom bits of the filter register certainly are.

I'm back working on something related, so may get a chance to study the actual stream in the near future.

Phil

I have now found time to set up the SPI slave to read in the raw modulator bit stream from the SD24 of a MSP430AFE253 set to maximum gain, bipolar input, low power, clocked at 1/2 MHz, while looking at input 7 (shorted).

It turns out to be a poor source of entropy.

The modulator is very aggressive about maintaining the 50% fraction of 1 bits, and it does so on a very short time scale. I expected a shortage of long runs, but in fact I saw only one run even as long as four bits in a row. Of the 256 possible byte values, I only ever saw 58 of them, and these were mostly the ones that strictly alternated (10101010 and 01010101 - most common) or nearly alternated but contained occasional 1100 or 0011 sequences (less than half as common). Less and less well balanced patterns were less and less common. So bytes grabbed from that raw stream do NOT have a flat distribution. Well, that is what the modulator is supposed to do - push the noise up to high frequencies, which in a bit stream must mean rapid alternation.

So you can't use that bit stream just raw as an entropy generator. However the same stream after passing through the filter gives an output very much like that of the SD16. At OSR=256, the low order byte of the filter register with LSBACC set to 1 has a nice flat distribution.